mirror of
https://github.com/sxpert/hp-saturn
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27 lines
640 B
Verilog
27 lines
640 B
Verilog
/******************************************************************************
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* 3n[xxxxxx] LC (n) [xxxxxx]
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*
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*
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*/
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`include "decstates.v"
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`DEC_LC_LEN: begin
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t_cnt <= nb_in;
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t_ctr <= 0;
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decstate <= `DEC_LC;
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end
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`DEC_LC: begin
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C[((t_ctr+P)%16)*4+:4] <= nb_in;
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if (t_ctr == t_cnt) begin
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decstate <= `DEC_START;
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`ifdef SIM
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$write("%5h LC (%h)\t%1h", inst_start_PC, t_cnt, nb_in);
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for(t_ctr = 0; t_ctr != t_cnt; t_ctr ++)
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$write("%1h", C[(((t_cnt - t_ctr - 4'h1)+P)%16)*4+:4]);
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$write("\n");
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`endif
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end else begin
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t_ctr <= (t_ctr + 1)&4'hf;
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end
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end
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