mirror of
https://github.com/sxpert/hp-saturn
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50 lines
No EOL
1.2 KiB
Verilog
50 lines
No EOL
1.2 KiB
Verilog
/******************************************************************************
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*1bnnnnn DO=(5) nnnnn
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*
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*
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*/
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`include "decstates.v"
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`DEC_D1_EQ_4N,
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`DEC_D0_EQ_5N, `DEC_D1_EQ_5N: begin
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case (decstate)
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`DEC_D1_EQ_4N: t_cnt <= 3;
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`DEC_D0_EQ_5N, `DEC_D1_EQ_5N: t_cnt <= 4;
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endcase
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t_ctr <= 1;
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case (decstate)
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`DEC_D0_EQ_5N: begin
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D0[3:0] <= nb_in;
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decstate <= `DEC_D0_EQ_LOOP;
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end
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`DEC_D1_EQ_4N, `DEC_D1_EQ_5N: begin
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D1[3:0] <= nb_in;
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decstate <= `DEC_D1_EQ_LOOP;
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end
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endcase
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end
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`DEC_D0_EQ_LOOP, `DEC_D1_EQ_LOOP: begin
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if (decstate == `DEC_D0_EQ_LOOP)
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D0[t_ctr*4+:4] <= nb_in;
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else
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D1[t_ctr*4+:4] <= nb_in;
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if (t_ctr == t_cnt) begin
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decstate <= `DEC_START;
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`ifdef SIM
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$write("%5h D%b=(%1d)\t%1h", inst_start_PC,
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(decstate == `DEC_D0_EQ_LOOP)?1'b0:1'b1,
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(t_cnt + 1), nb_in);
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for(t_ctr = 0; t_ctr != t_cnt; t_ctr ++)
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$write("%1h",
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(decstate == `DEC_D0_EQ_LOOP)?
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D0[(t_cnt - t_ctr - 4'h1)*4+:4]:
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D1[(t_cnt - t_ctr - 4'h1)*4+:4]
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);
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$write("\n");
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`endif
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end else
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t_ctr <= t_ctr + 1;
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end |