mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-27 09:58:16 +01:00
66 lines
1.1 KiB
Verilog
66 lines
1.1 KiB
Verilog
/******************************************************************************
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* 0X
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*
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*
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*/
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`DEC_0X: begin
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//generic RTN suff
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case (nb_in)
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4'h0, 4'h1, 4'h2, 4'h3: begin
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new_PC <= RSTK[rstk_ptr];
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RSTK[rstk_ptr] <= 0;
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rstk_ptr <= rstk_ptr - 1;
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next_cycle <= `BUSCMD_LOAD_PC;
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decstate <= `DEC_START;
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end
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default: begin end
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endcase
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// things specific to the
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case (nb_in)
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4'h0: begin
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HST[0] <= 1;
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`ifdef SIM
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$display("%05h RTNSXM", inst_start_PC);
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`endif
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end
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4'h1: begin
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`ifdef SIM
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$display("%05h RTN", inst_start_PC);
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`endif
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end
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4'h2: begin
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Carry <= 1;
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`ifdef SIM
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$display("%05h RTNSC", inst_start_PC);
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`endif
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end
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4'h3: begin
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Carry <= 0;
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`ifdef SIM
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$display("%05h RTNCC", inst_start_PC);
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`endif
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end
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4'h4: begin
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hex_dec <= `MODE_HEX;
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decstate <= `DEC_START;
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`ifdef SIM
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$display("%05h SETHEX", inst_start_PC);
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`endif
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end
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4'h5: begin
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hex_dec <= `MODE_DEC;
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decstate <= `DEC_START;
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`ifdef SIM
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$display("%05h SETDEC", inst_start_PC);
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`endif
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end
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default: begin
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$display("ERROR : DEC_0X");
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decode_error <= 1;
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end
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endcase
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end
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