7 commits

Author	SHA1	Message	Date
Raphael Jacquot	570807cf61	time to start over, this this is broken beyond fiddling	2019-02-24 21:54:15 +01:00
Raphael Jacquot	49b20d72f3	restore RTN / RTNCC / RTNSC	2019-02-23 06:57:48 +01:00
Raphael Jacquot	7376c920bc	change the clock phase generation from a counter to a shift register ... adapt everywhere needed	2019-02-22 19:30:53 +01:00
Raphael Jacquot	8725b736b5	attempt to change things according to ylamarre	2019-02-22 18:38:09 +01:00
Raphael Jacquot	390bdcd22f	simplify things in the ALU	2019-02-22 15:48:11 +01:00
Raphael Jacquot	93d786c2c1	alu rewrite in progress	2019-02-22 08:22:32 +01:00
Raphael Jacquot	30d7e6c8df	entirely rework the DP_WRITE and WRITE_DP case	2019-02-21 16:55:08 +01:00