12 commits

Author	SHA1	Message	Date
Raphael Jacquot	570807cf61	time to start over, this this is broken beyond fiddling	2019-02-24 21:54:15 +01:00
Raphael Jacquot	390bdcd22f	simplify things in the ALU	2019-02-22 15:48:11 +01:00
Raphael Jacquot	30d7e6c8df	entirely rework the DP_WRITE and WRITE_DP case	2019-02-21 16:55:08 +01:00
Raphael Jacquot	98d05d318f	add copyright and license (oops)	2019-02-20 09:15:22 +01:00
Raphael Jacquot	f1971c3bfe	add more instructions	2019-02-19 16:16:00 +01:00
Raphael Jacquot	0d3c3ecd3e	implement CONFIG ... cleanup the bus controller	2019-02-17 19:29:39 +01:00
Raphael Jacquot	7a3a36bd25	implement the reset bus command	2019-02-17 15:03:36 +01:00
Raphael Jacquot	781d15e0c7	hide some display instructions	2019-02-16 12:26:24 +01:00
Raphael Jacquot	ea3f53f70d	implement calculations for # test ... modify calculations for the unconditional jump and reload PC condition	2019-02-16 12:17:40 +01:00
Raphael Jacquot	06f79dca88	implemented decoding of 8Ax block, equality and inequality tests over ... field A. needs implementing the actual ALU op implemented RTNYES/GOYES((not totally finished) RTNYES works need to find an actual GOYES to test that	2019-02-16 11:08:34 +01:00
Raphael Jacquot	ef90d32971	handle block Cx ... add some code to handle goyes / rtnyes after the tests	2019-02-16 07:35:06 +01:00
Raphael Jacquot	343f1e2247	separate block 8 as it's going to be rather large	2019-02-15 11:04:01 +01:00