mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-26 09:58:09 +01:00
make it so that execution of bus programs happen
in the same cycle as the instruction modify the way jump and rtn are handled add some registers to the debugger
This commit is contained in:
Raphael Jacquot
parent
e97ec2243f
commit
c62d562008
5 changed files with 186 additions and 47 deletions
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@ -89,6 +89,7 @@ saturn_control_unit control_unit (
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.o_error (ctrl_unit_error),
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.o_alu_busy (alu_busy),
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.o_exec_unit_busy (exec_unit_busy),
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/* debugger interface */
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.o_current_pc (ctrl_current_pc),
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@ -122,6 +123,7 @@ wire [4:0] ctrl_unit_prog_data;
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wire [0:0] ctrl_unit_no_read;
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wire [0:0] alu_busy;
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wire [0:0] exec_unit_busy;
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/* debugger insterface */
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wire [19:0] ctrl_current_pc;
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@ -161,6 +163,7 @@ saturn_debugger debugger (
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.o_debug_cycle (dbg_debug_cycle),
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.i_alu_busy (alu_busy),
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.i_exec_unit_busy (exec_unit_busy),
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/* debugger interface */
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.i_current_pc (ctrl_current_pc),
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@ -44,6 +44,7 @@ module saturn_control_unit (
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/* alu is busy doing something */
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o_alu_busy,
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o_exec_unit_busy,
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/* debugger interface */
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@ -92,7 +93,14 @@ output wire [0:0] o_error;
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assign o_error = control_unit_error || dec_error;
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output wire [0:0] o_alu_busy;
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output wire [0:0] o_exec_unit_busy;
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assign o_alu_busy = inst_alu_other || alu_start;
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assign o_exec_unit_busy = i_bus_busy ||
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alu_busy ||
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jump_busy ||
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rtn_busy ||
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reset_busy ||
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config_busy;
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/* debugger interface */
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@ -153,6 +161,7 @@ saturn_inst_decoder instruction_decoder(
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.i_bus_busy (i_bus_busy),
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.i_alu_busy (o_alu_busy),
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.i_exec_unit_busy (o_exec_unit_busy),
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.i_nibble (i_nibble),
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.i_reg_p (reg_P),
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@ -203,6 +212,8 @@ wire [0:0] dec_error;
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wire [0:0] inst_alu = (dec_instr_type == `INSTR_TYPE_ALU);
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wire [0:0] inst_jump = (dec_instr_type == `INSTR_TYPE_JUMP);
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wire [0:0] inst_rtn = (dec_instr_type == `INSTR_TYPE_RTN);
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wire [0:0] inst_reset = (dec_instr_type == `INSTR_TYPE_RESET);
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wire [0:0] inst_config = (dec_instr_type == `INSTR_TYPE_CONFIG);
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wire [0:0] reg_dest_c = (dec_alu_reg_dest == `ALU_REG_C);
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wire [0:0] reg_dest_hst = (dec_alu_reg_dest == `ALU_REG_HST);
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@ -228,6 +239,12 @@ wire [0:0] inst_alu_other = inst_alu &&
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inst_alu_st_eq_01_n
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);
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wire [0:0] alu_busy = inst_alu_other || alu_start;
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wire [0:0] jump_busy = (inst_jump && dec_instr_decoded) || send_reg_PC;
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wire [0:0] rtn_busy = (inst_rtn && dec_instr_decoded) || send_reg_PC;
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wire [0:0] reset_busy = inst_reset;
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wire [0:0] config_busy = inst_config;
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/**************************************************************************************************
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*
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* PC and RSTK module
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@ -244,6 +261,7 @@ saturn_regs_pc_rstk regs_pc_rstk (
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.i_bus_busy (i_bus_busy),
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.i_alu_busy (o_alu_busy),
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.i_exec_unit_busy (o_exec_unit_busy),
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.i_nibble (i_nibble),
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.i_jump_instr (inst_jump),
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@ -379,6 +397,8 @@ reg [4:0] bus_program[0:31];
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reg [4:0] bus_prog_addr;
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reg [2:0] addr_nibble_ptr;
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reg [0:0] load_pc_loop;
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reg [0:0] send_reg_PC;
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reg [0:0] send_reg_C_A;
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reg [0:0] send_pc_read;
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@ -398,6 +418,8 @@ initial begin
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bus_prog_addr = 5'd0;
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addr_nibble_ptr = 3'd0;
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load_pc_loop = 1'b0;
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send_reg_PC = 1'b0;
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send_reg_C_A = 1'b0;
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send_pc_read = 1'b0;
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@ -432,18 +454,12 @@ always @(posedge i_clk) begin
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*
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*/
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if (i_clk_en && (just_reset || reload_PC) && i_phases[3]) begin
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if (i_clk_en && just_reset && i_phases[3]) begin
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/* this happend right after reset */
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if (just_reset) begin
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`ifdef SIM
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$display("CTRL %0d: [%d] we were just reset, loading PC", i_phase, i_cycle_ctr);
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`endif
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just_reset <= 1'b0;
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end else begin
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`ifdef SIM
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$display("CTRL %0d: [%d] reloading PC", i_phase, i_cycle_ctr);
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`endif
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end
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/* this loads the PC to the modules */
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bus_program[bus_prog_addr] <= {1'b1, `BUSCMD_LOAD_PC };
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`ifdef SIM
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@ -576,9 +592,14 @@ always @(posedge i_clk) begin
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`endif
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reg_alu_mode <= dec_alu_imm_value[0];
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end
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`INSTR_TYPE_JUMP: begin end
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`INSTR_TYPE_JUMP,
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`INSTR_TYPE_RTN:
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begin
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if (inst_jump) begin
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$display("CTRL %0d: [%d] JUMP", i_phase, i_cycle_ctr);
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end
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if (inst_rtn) begin
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$display("CTRL %0d: [%d] RTN", i_phase, i_cycle_ctr);
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case (dec_alu_opcode)
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`ALU_OP_SET_CRY: reg_CARRY <= o_alu_imm_value[0];
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default:
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@ -588,11 +609,21 @@ always @(posedge i_clk) begin
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end
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endcase
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end
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if (dec_instr_decoded) begin
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$display("CTRL %0d: [%d] exec : JUMP/RTN reload pc to %5h", i_phase, i_cycle_ctr, reg_PC);
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bus_program[bus_prog_addr] <= {1'b1, `BUSCMD_LOAD_PC };
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bus_prog_addr <= bus_prog_addr + 5'd1;
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addr_nibble_ptr <= 3'b0;
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send_reg_PC <= 1'b1;
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end
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end
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`INSTR_TYPE_LOAD:
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begin
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case (dec_alu_reg_dest)
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`ALU_REG_C: reg_C[dec_alu_ptr_begin] <= dec_alu_imm_value;
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`ALU_REG_D0: reg_D0[dec_alu_ptr_begin] <= dec_alu_imm_value;
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`ALU_REG_D0: reg_D0[dec_alu_ptr_begin[2:0]] <= dec_alu_imm_value;
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default:
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begin
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$display("CTRL %0d: [%d] unsupported register for load %0d", i_phase, i_cycle_ctr, dec_alu_reg_dest);
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@ -624,6 +655,27 @@ always @(posedge i_clk) begin
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endcase
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end
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end
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/**********************************************************************************************
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*
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* sending bus programs
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*
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*********************************************************************************************/
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if (i_clk_en && control_unit_ready) begin
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if (send_reg_PC) begin
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$display("CTRL %0d: [%d] exec: send_reg_PC[%0d] %h", i_phase, i_cycle_ctr, addr_nibble_ptr, reg_PC[addr_nibble_ptr*4+:4] );
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bus_program[bus_prog_addr] <= { 1'b0, reg_PC[addr_nibble_ptr*4+:4] };
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addr_nibble_ptr <= addr_nibble_ptr + 3'd1;
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bus_prog_addr <= bus_prog_addr + 5'd1;
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if (addr_nibble_ptr == 3'd4) begin
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addr_nibble_ptr <= 3'd0;
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send_reg_PC <= 1'b0;
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end
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end
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/*
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* send C(A)
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* used for CONFIG and UNCNFG
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@ -650,12 +702,17 @@ always @(posedge i_clk) begin
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end
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end
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/******************************************************************************************
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*
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* ALU control
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*
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*****************************************************************************************/
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if (i_clk_en && control_unit_ready) begin
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if (alu_start && alu_prep_run && !alu_prep_done) begin
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$display("ALU_PREP %0d: [%d] b %h | p %h | e %h", i_phase, i_cycle_ctr, alu_ptr_begin, alu_prep_pos, alu_ptr_end);
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@ -714,6 +771,8 @@ always @(posedge i_clk) begin
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bus_prog_addr <= 5'd0;
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addr_nibble_ptr <= 3'd0;
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load_pc_loop <= 1'b0;
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send_reg_PC <= 1'b0;
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send_reg_C_A <= 1'b0;
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send_pc_read <= 1'b0;
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@ -33,6 +33,7 @@ module saturn_debugger (
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o_debug_cycle,
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i_alu_busy,
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i_exec_unit_busy,
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/* interface from the control unit */
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i_current_pc,
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@ -81,6 +82,7 @@ input wire [31:0] i_cycle_ctr;
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output reg [0:0] o_debug_cycle;
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input wire [0:0] i_alu_busy;
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input wire [0:0] i_exec_unit_busy;
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/* inteface from the control unit */
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input wire [19:0] i_current_pc;
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@ -187,7 +189,7 @@ end
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always @(posedge i_clk) begin
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if (i_clk_en && i_phases[3] && i_instr_decoded && !debug_done && !i_alu_busy) begin
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if (i_clk_en && i_phases[3] && i_instr_decoded && !debug_done && !i_exec_unit_busy) begin
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$display("DEBUGGER %0d: [%d] start debugger cycle (alu_busy %b)", i_phase, i_cycle_ctr, i_alu_busy);
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o_debug_cycle <= 1'b1;
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registers_ctr <= 9'd0;
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@ -586,6 +588,65 @@ always @(posedge i_clk) begin
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if (registers_reg_ptr == 6'd0) begin
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registers_reg_ptr <= 6'd0;
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o_dbg_register <= `ALU_REG_NONE;
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registers_state <= `DBG_REG_R4_STR;
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end
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end
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`DBG_REG_R4_STR:
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begin
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case (registers_reg_ptr)
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6'd0: registers_str[registers_ctr] <= " ";
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6'd1: registers_str[registers_ctr] <= " ";
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6'd2: registers_str[registers_ctr] <= "R";
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6'd3: registers_str[registers_ctr] <= "4";
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6'd4: registers_str[registers_ctr] <= ":";
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6'd5: registers_str[registers_ctr] <= " ";
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6'd6: registers_str[registers_ctr] <= " ";
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default: begin end
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endcase
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd6) begin
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registers_reg_ptr <= 6'd15;
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o_dbg_register <= `ALU_REG_R4;
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registers_state <= `DBG_REG_R4_VALUE;
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end
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end
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`DBG_REG_R4_VALUE:
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begin
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registers_str[registers_ctr] <= hex[i_dbg_reg_nibble];
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registers_reg_ptr <= registers_reg_ptr - 6'd1;
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if (registers_reg_ptr == 6'd0) begin
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registers_reg_ptr <= 6'd0;
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o_dbg_register <= `ALU_REG_NONE;
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registers_state <= `DBG_REG_RSTK1_STR;
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end
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end
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`DBG_REG_RSTK1_STR:
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begin
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case (registers_reg_ptr)
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6'd0: registers_str[registers_ctr] <= " ";
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6'd1: registers_str[registers_ctr] <= " ";
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6'd2: registers_str[registers_ctr] <= "R";
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6'd3: registers_str[registers_ctr] <= "S";
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6'd4: registers_str[registers_ctr] <= "T";
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6'd5: registers_str[registers_ctr] <= "K";
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6'd6: registers_str[registers_ctr] <= "1";
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6'd7: registers_str[registers_ctr] <= ":";
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6'd8: registers_str[registers_ctr] <= " ";
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default: begin end
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endcase
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registers_reg_ptr <= registers_reg_ptr + 6'd1;
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if (registers_reg_ptr == 6'd8) begin
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registers_reg_ptr <= 6'd4;
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o_dbg_rstk_ptr <= 3'd1;
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registers_state <= `DBG_REG_RSTK1_VALUE;
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end
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end
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`DBG_REG_RSTK1_VALUE:
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begin
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registers_str[registers_ctr] <= hex[i_dbg_rstk_val[(registers_reg_ptr)*4+:4]];
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registers_reg_ptr <= registers_reg_ptr - 6'd1;
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if (registers_reg_ptr == 6'd0) begin
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registers_reg_ptr <= 6'd0;
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registers_state <= `DBG_REG_SPACES_7;
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end
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end
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@ -32,6 +32,7 @@ module saturn_inst_decoder (
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i_bus_busy,
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i_alu_busy,
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i_exec_unit_busy,
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i_nibble,
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i_reg_p,
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@ -70,6 +71,7 @@ input wire [31:0] i_cycle_ctr;
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input wire [0:0] i_bus_busy;
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input wire [0:0] i_alu_busy;
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input wire [0:0] i_exec_unit_busy;
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input wire [3:0] i_nibble;
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input wire [3:0] i_reg_p;
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@ -235,7 +237,7 @@ always @(posedge i_clk) begin
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o_instr_decoded <= 1'b1;
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end
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if (i_clk_en && !i_bus_busy && !i_alu_busy) begin
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if (i_clk_en && !i_bus_busy && !i_exec_unit_busy) begin
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if (i_phases[1] && !decode_started) begin
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// $display("DECODER %0d: [%d] store current PC as instruction start %5h", i_phase, i_cycle_ctr, i_current_pc);
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@ -30,6 +30,7 @@ module saturn_regs_pc_rstk (
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i_bus_busy,
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i_alu_busy,
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i_exec_unit_busy,
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i_nibble,
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i_jump_instr,
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@ -56,6 +57,7 @@ input wire [31:0] i_cycle_ctr;
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input wire [0:0] i_bus_busy;
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input wire [0:0] i_alu_busy;
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input wire [0:0] i_exec_unit_busy;
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input wire [3:0] i_nibble;
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input wire [0:0] i_jump_instr;
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@ -152,7 +154,7 @@ always @(posedge i_clk) begin
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// if (!i_debug_cycle)
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// $display("PC_RSTK %0d: [%d] !i_bus_busy %b", i_phase, i_cycle_ctr, !i_bus_busy);
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if (i_clk_en && !i_bus_busy && !i_alu_busy) begin
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if (i_clk_en && !i_bus_busy && !i_exec_unit_busy) begin
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if (i_phases[3] && just_reset) begin
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$display("PC_RSTK %0d: [%d] exit from reset mode", i_phase, i_cycle_ctr);
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@ -168,8 +170,12 @@ always @(posedge i_clk) begin
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* jump instruction calculations
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*/
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/* start the jump instruction */
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if (i_phases[3] && do_jump_instr && !jump_decode && !jump_exec) begin
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/* start the jump instruction
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* the jump base is:
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* address of first nibble of the offset when goto
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* address of nibble after the offset when gosub
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*/
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if (i_phases[3] && do_jump_instr && !jump_decode) begin
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$display("PC_RSTK %0d: [%d] start decode jump %0d | jump_base %5h", i_phase, i_cycle_ctr, i_jump_length, reg_PC);
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jump_counter <= 3'd0;
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jump_base <= reg_PC;
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@ -182,25 +188,33 @@ always @(posedge i_clk) begin
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jump_offset <= jump_next_offset;
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jump_counter <= jump_counter + 3'd1;
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if (jump_counter == i_jump_length) begin
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$write("PC_RSTK %0d: [%d] execute jump(%0d) jump_base %h jump_next_offset %h", i_phase, i_cycle_ctr, i_jump_length, jump_base, jump_next_offset);
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jump_decode <= 1'b0;
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jump_exec <= 1'b1;
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o_reload_pc <= 1'b1;
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end
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end
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/* all done, apply to PC and RSTK */
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if (i_phases[3] && do_jump_instr && jump_exec) begin
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$write("PC_RSTK %0d: [%d] execute jump %0d", i_phase, i_cycle_ctr, i_jump_length);
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// jump_exec <= 1'b1;
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// o_reload_pc <= 1'b1;
|
||||
reg_PC <= jump_relative ? jump_next_offset + jump_base : jump_next_offset;
|
||||
if (i_push_pc) begin
|
||||
$write(" ( push %5h => RSTK[%0d])", reg_PC, reg_rstk_ptr + 3'd1);
|
||||
$write(" ( push %5h => RSTK[%0d] )", reg_PC, reg_rstk_ptr + 3'd1);
|
||||
reg_RSTK[(reg_rstk_ptr + 3'o1)&3'o7] <= reg_PC;
|
||||
reg_rstk_ptr <= reg_rstk_ptr + 3'd1;
|
||||
end
|
||||
$display("");
|
||||
reg_PC <= jump_relative ? jump_offset + jump_base : jump_offset;
|
||||
jump_exec <= 1'b0;
|
||||
o_reload_pc <= 1'b0;
|
||||
$write("\n");
|
||||
end
|
||||
end
|
||||
|
||||
// /* all done, apply to PC and RSTK */
|
||||
// if (i_phases[3] && do_jump_instr && jump_exec) begin
|
||||
// $write("PC_RSTK %0d: [%d] execute jump %0d", i_phase, i_cycle_ctr, i_jump_length);
|
||||
// if (i_push_pc) begin
|
||||
// $write(" ( push %5h => RSTK[%0d])", reg_PC, reg_rstk_ptr + 3'd1);
|
||||
// reg_RSTK[(reg_rstk_ptr + 3'o1)&3'o7] <= reg_PC;
|
||||
// reg_rstk_ptr <= reg_rstk_ptr + 3'd1;
|
||||
// end
|
||||
// $display("");
|
||||
// reg_PC <= jump_relative ? jump_offset + jump_base : jump_offset;
|
||||
// jump_exec <= 1'b0;
|
||||
// o_reload_pc <= 1'b0;
|
||||
// end
|
||||
|
||||
/*
|
||||
* RTN instruction
|
||||
|
|
@ -216,7 +230,7 @@ always @(posedge i_clk) begin
|
|||
4'h3: $display("CC");
|
||||
default: begin end
|
||||
endcase
|
||||
o_reload_pc <= 1'b1;
|
||||
// o_reload_pc <= 1'b1;
|
||||
end
|
||||
|
||||
if (i_phases[3] && i_rtn_instr) begin
|
||||
|
|
@ -225,7 +239,7 @@ always @(posedge i_clk) begin
|
|||
reg_RSTK[reg_rstk_ptr] <= 20'h00000;
|
||||
reg_rstk_ptr <= (reg_rstk_ptr - 3'd1) & 3'd7;
|
||||
/* o_reload_pc was set in advance above */
|
||||
o_reload_pc <= 1'b0;
|
||||
// o_reload_pc <= 1'b0;
|
||||
end
|
||||
|
||||
end
|
||||
|
|
|
|||
Loading…
Reference in a new issue