test of new decoder structure

saturn-decoder.v

@@ -0,0 +1,86 @@
+/******************************************************************************
+ *
+ * Instruction decoder module
+ *
+ *****************************************************************************/
+
+module saturn_decoder(
+     i_clk, 
+     i_reset,
+     i_cycles,
+     i_en_dec,
+     i_en_exec,
+    //  i_stalled,
+     i_nibble);
+
+/*
+ * module input / output ports
+ */
+input   wire        i_clk;
+input   wire        i_reset;
+input   wire [31:0] i_cycles;
+input   wire        i_en_dec;
+input   wire        i_en_exec;
+// input   wire            i_stalled;
+input   wire [3:0]  i_nibble;
+
+/*
+ * state registers
+ */
+
+reg         continue;
+wire        instr_start;
+reg [31:0]  instr_ctr;
+
+initial begin
+  continue = 0;
+  $monitor({"i_clk %b | i_reset %b | i_cycles %d | i_en_dec %b | i_en_exec %b |",
+           " continue %b | instr_start %b | i_nibble %h | block_0x %b | ins_rtnsxm %b"}, 
+           i_clk, i_reset, i_cycles, i_en_dec, i_en_exec, continue, 
+           instr_start, i_nibble, block_0x, ins_rtnsxm);
+end
+
+/*
+ * handle the fist nibble decoding
+ * that's pretty simple though, will get tougher later on :-)
+ */
+
+reg block_0x;
+
+assign instr_start = ~continue || i_reset;
+
+always @(posedge i_clk) begin
+  if (i_reset) begin
+    block_0x <= 0;
+  end else begin
+    if (instr_start && i_en_dec) begin
+      continue <= 1;
+      // assign block regs
+      block_0x <= (i_nibble == 4'h0);
+    end
+  end
+end
+
+/*
+ * handle block 0
+ */
+
+reg ins_rtnsxm;
+
+always @(posedge i_clk) begin
+  if (i_reset) begin
+    ins_rtnsxm <= 0;
+  end else begin
+    if (continue && i_en_dec && block_0x) begin
+      ins_rtnsxm <= (i_nibble == 4'h0);
+    end
+  end
+end
+
+always @(posedge i_clk) begin
+  if (i_en_exec && ins_rtnsxm)
+    $display("do something");
+end
+
+
+endmodule

saturn_core.v

@@ -4,9 +4,10 @@
 
 `default_nettype none //
 
-`include "bus_commands.v"
-`include "hp48_00_bus.v"
-`include "dbg_module.v"
+// `include "bus_commands.v"
+// `include "hp48_00_bus.v"
+// `include "dbg_module.v"
+`include "saturn-decoder.v"
 
 /**************************************************************************************************
  *
@@ -67,6 +68,16 @@ wire			halt;
 // 	.bus_error		(bus_error)
 // );
 
+saturn_decoder i_decoder (
+	.i_clk		(clk),
+	.i_reset	(reset),
+	.i_cycles	(cycle_ctr),
+	.i_en_dec	(en_inst_dec),
+	.i_en_exec  (en_inst_exec),
+	// .i_stalled	(stalled),
+	.i_nibble	(nibble_in)
+);
+
 initial
 	begin
 		clk_phase 				= 0;
@@ -129,10 +140,19 @@ always @(posedge clk) begin
 	end
 end
 
-always @(posedge clk) 
-	if (en_debugger)
-		$display(cycle_ctr);
+// always @(posedge clk) 
+// 	if (en_debugger)
+// 		$display(cycle_ctr);
 
+reg [3:0] nibble_in;
+
+always @(posedge clk)
+	if (en_bus_recv)
+		case (cycle_ctr)
+		0:	nibble_in <= 0;
+		1:  nibble_in <= 0;
+		2:  clock_end <= 1;
+		endcase
 
 assign halt = clock_end;