mirror of
https://github.com/sxpert/hp-saturn
synced 2025-01-05 11:01:48 +01:00
86 lines
No EOL
1.7 KiB
Verilog
86 lines
No EOL
1.7 KiB
Verilog
/******************************************************************************
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*
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* Instruction decoder module
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*
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*****************************************************************************/
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module saturn_decoder(
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i_clk,
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i_reset,
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i_cycles,
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i_en_dec,
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i_en_exec,
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// i_stalled,
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i_nibble);
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/*
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* module input / output ports
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*/
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input wire i_clk;
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input wire i_reset;
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input wire [31:0] i_cycles;
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input wire i_en_dec;
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input wire i_en_exec;
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// input wire i_stalled;
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input wire [3:0] i_nibble;
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/*
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* state registers
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*/
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reg continue;
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wire instr_start;
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reg [31:0] instr_ctr;
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initial begin
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continue = 0;
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$monitor({"i_clk %b | i_reset %b | i_cycles %d | i_en_dec %b | i_en_exec %b |",
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" continue %b | instr_start %b | i_nibble %h | block_0x %b | ins_rtnsxm %b"},
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i_clk, i_reset, i_cycles, i_en_dec, i_en_exec, continue,
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instr_start, i_nibble, block_0x, ins_rtnsxm);
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end
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/*
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* handle the fist nibble decoding
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* that's pretty simple though, will get tougher later on :-)
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*/
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reg block_0x;
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assign instr_start = ~continue || i_reset;
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always @(posedge i_clk) begin
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if (i_reset) begin
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block_0x <= 0;
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end else begin
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if (instr_start && i_en_dec) begin
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continue <= 1;
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// assign block regs
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block_0x <= (i_nibble == 4'h0);
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end
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end
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end
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/*
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* handle block 0
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*/
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reg ins_rtnsxm;
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always @(posedge i_clk) begin
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if (i_reset) begin
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ins_rtnsxm <= 0;
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end else begin
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if (continue && i_en_dec && block_0x) begin
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ins_rtnsxm <= (i_nibble == 4'h0);
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end
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end
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end
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always @(posedge i_clk) begin
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if (i_en_exec && ins_rtnsxm)
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$display("do something");
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end
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endmodule |