Miroirs/hp-saturn
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Raphael Jacquot 2019-02-06 10:40:55 +01:00
parent 11d3d1dfef
commit 82f4df8e93
8 changed files with 67 additions and 18461 deletions
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3
README Normal file
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Verilog implementation of the HP saturn processor
licence: GPLv3 or later

6
compile
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#!/bin/bash #!/bin/bash
#yosys -p "synth_ecp5 -top mask_gen -json mask_gen.json" mask_gen.v #
#nextpnr-ecp5 --gui --um-85k --speed 6 --freq 5 --json mask_gen.json --save mask_gen.ecp5 # licence: GPLv3 or later
#
yosys -p "synth_ecp5 -top saturn_core -json saturn_core.json" saturn_core.v yosys -p "synth_ecp5 -top saturn_core -json saturn_core.json" saturn_core.v
nextpnr-ecp5 --gui --85k --speed 6 --freq 5 --lpf ulx3s_v20.lpf --textcfg empty_lfe5u-85f.config --json saturn_core.json --save saturn_core.ecp5 nextpnr-ecp5 --gui --85k --speed 6 --freq 5 --lpf ulx3s_v20.lpf --textcfg empty_lfe5u-85f.config --json saturn_core.json --save saturn_core.ecp5

3
gen_rom_hex.py
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#!/usr/bin/env python3 #!/usr/bin/env python3
#
# licence: GPLv3 or later
#
f = open("../docs/gxrom-r", "rb") f = open("../docs/gxrom-r", "rb")
count=0 count=0

17634
mask_gen.json
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File diff suppressed because it is too large Load diff

164
mask_gen.v
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module mask_gen (
// ports
clk,
nibble_width,
nibble_start,
mask
);
input clk; // clock
input wire [3:0] nibble_width; // length of mask in nibbles
input wire [3:0] nibble_start; // nibble where the mask starts
output reg [63:0] mask;// 64 bits mask
reg [4:0] n_max;
wire [3:0] nm1 = n_max[3:0];
reg [15:0] bitmask_1;
reg [15:0] bitmask_2;
reg [15:0] bitmask;
//wire [3:0] nm1;
always @( posedge clk) begin
bitmask_1[ 0] = nibble_start==0;
bitmask_1[ 1] = nibble_start==1 | bitmask_1[0];
bitmask_1[ 2] = nibble_start==2 | bitmask_1[1];
bitmask_1[ 3] = nibble_start==3 | bitmask_1[2];
bitmask_1[ 4] = nibble_start==4 | bitmask_1[3];
bitmask_1[ 5] = nibble_start==5 | bitmask_1[4];
bitmask_1[ 6] = nibble_start==6 | bitmask_1[5];
bitmask_1[ 7] = nibble_start==7 | bitmask_1[6];
bitmask_1[ 8] = nibble_start==8 | bitmask_1[7];
bitmask_1[ 9] = nibble_start==9 | bitmask_1[8];
bitmask_1[10] = nibble_start==10 | bitmask_1[9];
bitmask_1[11] = nibble_start==11 | bitmask_1[10];
bitmask_1[12] = nibble_start==12 | bitmask_1[11];
bitmask_1[13] = nibble_start==13 | bitmask_1[12];
bitmask_1[14] = nibble_start==14 | bitmask_1[13];
bitmask_1[15] = nibble_start==15 | bitmask_1[14];
$display("bm1 : %b", bitmask_1);
n_max <= nibble_start + nibble_width + 1;
$display("n_max : %h", n_max);
//nm1[3:0] = n_max[3:0];
bitmask_2[15] = nm1==15;
bitmask_2[14] = nm1==14 | bitmask_2[15];
bitmask_2[13] = nm1==13 | bitmask_2[14];
bitmask_2[12] = nm1==12 | bitmask_2[13];
bitmask_2[11] = nm1==11 | bitmask_2[12];
bitmask_2[10] = nm1==10 | bitmask_2[11];
bitmask_2[ 9] = nm1==9 | bitmask_2[10];
bitmask_2[ 8] = nm1==8 | bitmask_2[9];
bitmask_2[ 7] = nm1==7 | bitmask_2[8];
bitmask_2[ 6] = nm1==6 | bitmask_2[7];
bitmask_2[ 5] = nm1==5 | bitmask_2[6];
bitmask_2[ 4] = nm1==4 | bitmask_2[5];
bitmask_2[ 3] = nm1==3 | bitmask_2[4];
bitmask_2[ 2] = nm1==2 | bitmask_2[3];
bitmask_2[ 1] = nm1==1 | bitmask_2[2];
bitmask_2[ 0] = nm1==0 | bitmask_2[1];
$display("bm2 : %b", bitmask_2);
bitmask = n_max[4] ? bitmask_1 | bitmask_2 : bitmask_1 & bitmask_2;
$display("bm : %b", bitmask);
mask[ 3: 0] = {4{bitmask[ 0]}};
mask[ 7: 4] = {4{bitmask[ 1]}};
mask[11: 8] = {4{bitmask[ 2]}};
mask[15:12] = {4{bitmask[ 3]}};
mask[19:16] = {4{bitmask[ 4]}};
mask[23:20] = {4{bitmask[ 5]}};
mask[27:24] = {4{bitmask[ 6]}};
mask[31:28] = {4{bitmask[ 7]}};
mask[35:32] = {4{bitmask[ 8]}};
mask[39:36] = {4{bitmask[ 9]}};
mask[43:40] = {4{bitmask[10]}};
mask[47:44] = {4{bitmask[11]}};
mask[51:48] = {4{bitmask[12]}};
mask[55:52] = {4{bitmask[13]}};
mask[59:56] = {4{bitmask[14]}};
mask[63:60] = {4{bitmask[15]}};
end
endmodule
`ifdef SIM
//`timescale 1 ns / 100 ps
module mask_gen_tb;
// inputs
reg clock;
reg [3:0] nw;
reg [3:0] ns;
// outputs
wire [63:0] m;
mask_gen U0 (
.clk (clock),
.nibble_width (nw),
.nibble_start (ns),
.mask (m)
);
always
#10 clock = (clock === 1'b0);
initial begin
//$monitor ("clk %b", clock);
$monitor ("clk %b | nw %d | ns %d | m %h", clock, nw, ns, m);
//#10 $display("1");
//#10 $display("2");
//#10 $finish;
end
initial begin
$dumpfile("text.vcd");
$dumpvars(clock, nw, ns, m);
$display($time, "starting simulation");
clock = 0;
$display("starting the simulation");
run_mask_gen(4, 0);
run_mask_gen(4, 1);
run_mask_gen(4, 2);
run_mask_gen(4, 3);
run_mask_gen(4, 4);
run_mask_gen(4, 5);
run_mask_gen(4, 6);
run_mask_gen(4, 7);
run_mask_gen(4, 8);
run_mask_gen(4, 9);
run_mask_gen(4,10);
run_mask_gen(4,11);
run_mask_gen(4,12);
run_mask_gen(4,13);
run_mask_gen(4,14);
run_mask_gen(4,15);
//run_mask_gen(4, 0);
//run_mask_gen(4, 0);
//run_mask_gen(4, 0);
//run_mask_gen(4, 0);
$finish;
end
task run_mask_gen;
input [3:0] _nw;
input [3:0] _ns;
begin
$display("running", _nw, _ns);
@(posedge clock);
nw = _nw;
ns = _ns;
end
endtask
endmodule
`endif

645
mask_gen_tb
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#! /usr/bin/vvp -v
:ivl_version "10.1 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "vhdl_sys";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0x562a0b875c60 .scope module, "mask_gen_tb" "mask_gen_tb" 2 89;
.timescale 0 0;
v0x562a0b8968d0_0 .var "clock", 0 0;
v0x562a0b896990_0 .net "m", 63 0, v0x562a0b896040_0; 1 drivers
v0x562a0b896a60_0 .var "ns", 3 0;
v0x562a0b896b60_0 .var "nw", 3 0;
S_0x562a0b875de0 .scope module, "U0" "mask_gen" 2 100, 2 1 0, S_0x562a0b875c60;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk"
.port_info 1 /INPUT 4 "nibble_width"
.port_info 2 /INPUT 4 "nibble_start"
.port_info 3 /OUTPUT 64 "mask"
v0x562a0b85f770_0 .var "bitmask", 15 0;
v0x562a0b895de0_0 .var "bitmask_1", 15 0;
v0x562a0b895ec0_0 .var "bitmask_2", 15 0;
v0x562a0b895f80_0 .net "clk", 0 0, v0x562a0b8968d0_0; 1 drivers
v0x562a0b896040_0 .var "mask", 63 0;
v0x562a0b896170_0 .var "n_max", 4 0;
v0x562a0b896250_0 .net "nibble_start", 3 0, v0x562a0b896a60_0; 1 drivers
v0x562a0b896330_0 .net "nibble_width", 3 0, v0x562a0b896b60_0; 1 drivers
v0x562a0b896410_0 .net "nm1", 3 0, L_0x562a0b896c30; 1 drivers
E_0x562a0b8468f0 .event posedge, v0x562a0b895f80_0;
L_0x562a0b896c30 .part v0x562a0b896170_0, 0, 4;
S_0x562a0b896570 .scope task, "run_mask_gen" "run_mask_gen" 2 151, 2 151 0, S_0x562a0b875c60;
.timescale 0 0;
v0x562a0b896710_0 .var "_ns", 3 0;
v0x562a0b8967f0_0 .var "_nw", 3 0;
TD_mask_gen_tb.run_mask_gen ;
%vpi_call 2 155 "$display", "running", v0x562a0b8967f0_0, v0x562a0b896710_0 {0 0 0};
%wait E_0x562a0b8468f0;
%load/vec4 v0x562a0b8967f0_0;
%store/vec4 v0x562a0b896b60_0, 0, 4;
%load/vec4 v0x562a0b896710_0;
%store/vec4 v0x562a0b896a60_0, 0, 4;
%end;
.scope S_0x562a0b875de0;
T_1 ;
%wait E_0x562a0b8468f0;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 1, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 0, 2;
%or;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 2, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 1, 2;
%or;
%ix/load 4, 2, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 3, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 2, 3;
%or;
%ix/load 4, 3, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 4, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 3, 3;
%or;
%ix/load 4, 4, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 5, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 4, 4;
%or;
%ix/load 4, 5, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 6, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 5, 4;
%or;
%ix/load 4, 6, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 7, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 6, 4;
%or;
%ix/load 4, 7, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 8, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 7, 4;
%or;
%ix/load 4, 8, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 9, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 8, 5;
%or;
%ix/load 4, 9, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 10, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 9, 5;
%or;
%ix/load 4, 10, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 11, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 10, 5;
%or;
%ix/load 4, 11, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 12, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 11, 5;
%or;
%ix/load 4, 12, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 13, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 12, 5;
%or;
%ix/load 4, 13, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 14, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 13, 5;
%or;
%ix/load 4, 14, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 15, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 14, 5;
%or;
%ix/load 4, 15, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%vpi_call 2 37 "$display", "bm1 : %b", v0x562a0b895de0_0 {0 0 0};
%load/vec4 v0x562a0b896250_0;
%pad/u 5;
%load/vec4 v0x562a0b896330_0;
%pad/u 5;
%add;
%addi 1, 0, 5;
%assign/vec4 v0x562a0b896170_0, 0;
%vpi_call 2 41 "$display", "n_max : %h", v0x562a0b896170_0 {0 0 0};
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 15, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%ix/load 4, 15, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 14, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 15, 5;
%or;
%ix/load 4, 14, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 13, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 14, 5;
%or;
%ix/load 4, 13, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 12, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 13, 5;
%or;
%ix/load 4, 12, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 11, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 12, 5;
%or;
%ix/load 4, 11, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 10, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 11, 5;
%or;
%ix/load 4, 10, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 9, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 10, 5;
%or;
%ix/load 4, 9, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 8, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 9, 5;
%or;
%ix/load 4, 8, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 7, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 8, 5;
%or;
%ix/load 4, 7, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 6, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 7, 4;
%or;
%ix/load 4, 6, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 5, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 6, 4;
%or;
%ix/load 4, 5, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 4, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 5, 4;
%or;
%ix/load 4, 4, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 3, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 4, 4;
%or;
%ix/load 4, 3, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 2, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 3, 3;
%or;
%ix/load 4, 2, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 1, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 2, 3;
%or;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 1, 2;
%or;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%vpi_call 2 60 "$display", "bm2 : %b", v0x562a0b895ec0_0 {0 0 0};
%load/vec4 v0x562a0b896170_0;
%parti/s 1, 4, 4;
%flag_set/vec4 8;
%jmp/0 T_1.0, 8;
%load/vec4 v0x562a0b895de0_0;
%load/vec4 v0x562a0b895ec0_0;
%or;
%jmp/1 T_1.1, 8;
T_1.0 ; End of true expr.
%load/vec4 v0x562a0b895de0_0;
%load/vec4 v0x562a0b895ec0_0;
%and;
%jmp/0 T_1.1, 8;
; End of false expr.
%blend;
T_1.1;
%store/vec4 v0x562a0b85f770_0, 0, 16;
%vpi_call 2 63 "$display", "bm : %b", v0x562a0b85f770_0 {0 0 0};
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 0, 2;
%replicate 4;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 1, 2;
%replicate 4;
%ix/load 4, 4, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 2, 3;
%replicate 4;
%ix/load 4, 8, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 3, 3;
%replicate 4;
%ix/load 4, 12, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 4, 4;
%replicate 4;
%ix/load 4, 16, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 5, 4;
%replicate 4;
%ix/load 4, 20, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 6, 4;
%replicate 4;
%ix/load 4, 24, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 7, 4;
%replicate 4;
%ix/load 4, 28, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 8, 5;
%replicate 4;
%ix/load 4, 32, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 9, 5;
%replicate 4;
%ix/load 4, 36, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 10, 5;
%replicate 4;
%ix/load 4, 40, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 11, 5;
%replicate 4;
%ix/load 4, 44, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 12, 5;
%replicate 4;
%ix/load 4, 48, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 13, 5;
%replicate 4;
%ix/load 4, 52, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 14, 5;
%replicate 4;
%ix/load 4, 56, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 15, 5;
%replicate 4;
%ix/load 4, 60, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%jmp T_1;
.thread T_1;
.scope S_0x562a0b875c60;
T_2 ;
%delay 10, 0;
%load/vec4 v0x562a0b8968d0_0;
%pushi/vec4 0, 0, 1;
%cmp/e;
%flag_get/vec4 6;
%store/vec4 v0x562a0b8968d0_0, 0, 1;
%jmp T_2;
.thread T_2;
.scope S_0x562a0b875c60;
T_3 ;
%vpi_call 2 113 "$monitor", "clk %b | nw %d | ns %d | m %h", v0x562a0b8968d0_0, v0x562a0b896b60_0, v0x562a0b896a60_0, v0x562a0b896990_0 {0 0 0};
%end;
.thread T_3;
.scope S_0x562a0b875c60;
T_4 ;
%vpi_call 2 121 "$dumpfile", "text.vcd" {0 0 0};
%vpi_call 2 122 "$dumpvars", v0x562a0b8968d0_0, v0x562a0b896b60_0, v0x562a0b896a60_0, v0x562a0b896990_0 {0 0 0};
%vpi_call 2 123 "$display", $time, "starting simulation" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x562a0b8968d0_0, 0, 1;
%vpi_call 2 125 "$display", "starting the simulation" {0 0 0};
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 3, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 5, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 6, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 7, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 8, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 9, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 10, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 11, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 12, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 13, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 14, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%vpi_call 2 147 "$finish" {0 0 0};
%end;
.thread T_4;
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
"mask_gen.v";

3
run
View file

@ -1,4 +1,7 @@
#!/bin/bash #!/bin/bash
#
# licence: GPLv3 or later
#
verilator -Wall -cc saturn_core.v verilator -Wall -cc saturn_core.v
VERILATOR_STATUS=$? VERILATOR_STATUS=$?
if [ "VERILATOR_STATUS" != "0" ] if [ "VERILATOR_STATUS" != "0" ]

62
saturn_core.v
View file

@ -1,3 +1,7 @@
/*
* Licence: GPLv3 or later
*/
`default_nettype none // `default_nettype none //
/************************************************************************************************** /**************************************************************************************************
@ -43,18 +47,25 @@ endmodule
* *
* *
*/ */
`define BUSCMD_NOP 0
`define BUSCMD_DP_WRITE 5
`define BUSCMD_CONFIGURE 8
module hp48_io_ram ( module hp48_io_ram (
input clk, input clk,
input [19:0] address, input [19:0] address,
input configure, input [3:0] command,
input write,
input [3:0] nibble_in, input [3:0] nibble_in,
output [3:0] nibble_out output [3:0] nibble_out
); );
localparam IO_RAM_LEN = 64; localparam IO_RAM_LEN = 64;
// localparam BUSCMD_DP_WRITE = C_BUSCMD_DP_WRITE;
// localparam BUSCMD_CONFIGURE = C_BUSCMD_CONFIGURE;
reg configured; reg configured;
reg [19:0] base_addr; reg [19:0] base_addr;
reg [3:0] io_ram [0:IO_RAM_LEN-1]; reg [3:0] io_ram [0:IO_RAM_LEN-1];
@ -85,8 +96,19 @@ initial
`endif `endif
end end
//always @(posedge clk) always @(posedge clk)
case (command)
`BUSCMD_NOP: begin end // do nothing
`BUSCMD_CONFIGURE:
begin
`ifdef SIM
$display("io_ram: configure at %5h len %d", address, IO_RAM_LEN);
`endif
base_addr <= address;
end
default:
$display("io_ram: unhandled command %h", command);
endcase
endmodule endmodule
@ -128,6 +150,11 @@ assign reset = btn[1];
localparam REGDMP_HEX = 8'h00; localparam REGDMP_HEX = 8'h00;
// bus commands
// localparam BUSCMD_DP_WRITE = `C_BUSCMD_DP_WRITE;
// localparam BUSCMD_CONFIGURE = `C_BUSCMD_CONFIGURE;
// runstate // runstate
localparam RUN_START = 0; localparam RUN_START = 0;
@ -222,8 +249,7 @@ reg rom_enable;
wire[3:0] rom_nibble; wire[3:0] rom_nibble;
// io_ram access // io_ram access
reg io_configure; reg [3:0] bus_command;
reg io_write;
reg [3:0] nibble_in; reg [3:0] nibble_in;
wire [3:0] nibble_out; wire [3:0] nibble_out;
@ -275,8 +301,7 @@ hp_rom calc_rom (
hp48_io_ram io_ram ( hp48_io_ram io_ram (
.clk (clk), .clk (clk),
.address (rom_address), .address (rom_address),
.configure (io_configure), .command (bus_command),
.write (io_write),
.nibble_in (nibble_in), .nibble_in (nibble_in),
.nibble_out (nibble_out) .nibble_out (nibble_out)
); );
@ -291,6 +316,19 @@ begin
if (reset) if (reset)
begin begin
// bus
bus_command <= `BUSCMD_NOP;
// processor state machine
halt <= 0;
runstate <= RUN_START;
decstate <= DECODE_START;
regdump <= REGDMP_HEX;
// processor registers
hex_dec <= HEX; hex_dec <= HEX;
rstk_ptr <= 7; rstk_ptr <= 7;
@ -323,10 +361,6 @@ begin
R3 <= 0; R3 <= 0;
R4 <= 0; R4 <= 0;
halt <= 0;
runstate <= RUN_START;
decstate <= DECODE_START;
regdump <= REGDMP_HEX;
end end
else else
if (runstate == RUN_START) if (runstate == RUN_START)
@ -389,6 +423,10 @@ begin
runstate <= READ_ROM_VAL; runstate <= READ_ROM_VAL;
end end
if (runstate == WRITE_STA)
begin
bus_command <= `BUSCMD_DP_WRITE;
end
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
// //