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fix bus debugger for read program
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parent
dd9faf509e
commit
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2 changed files with 8 additions and 6 deletions
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@ -237,7 +237,7 @@ always @(posedge i_clk) begin
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end
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`ifdef SIM
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if (cycle_ctr == 320) begin
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if (cycle_ctr == 370) begin
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bus_halt <= 1'b1;
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$display("BUS %0d: [%d] enough cycles for now", phase, cycle_ctr);
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end
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@ -289,10 +289,12 @@ always @(posedge i_clk) begin
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bus_busy <= 1'b1;
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/* data for the debugger */
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if (!ctrl_unit_prog_data[5]) begin
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dbg_bus_info <= 1'b1;
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dbg_bus_action <= { 1'b0, ctrl_unit_prog_data[4]};
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dbg_bus_data <= ctrl_unit_prog_data[3:0];
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end
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end
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/*
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* nothing to send, see if we can read, and do it
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*/
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@ -324,8 +326,8 @@ always @(posedge i_clk) begin
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bus_busy <= 1'b0;
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end
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/* at that poing, weread data in for the debugger */
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if (!bus_busy && !alu_busy) begin
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/* at that poing, we read data in for the debugger */
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if ((!bus_busy && !alu_busy) || bus_read) begin
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dbg_bus_info <= 1'b1;
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dbg_bus_action <= 2'b10;
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dbg_bus_data <= i_bus_nibble_in;
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