export rstk_ptr to debugger

implement LCHEX (and almost done for LAHEX)

saturn_bus.v

@@ -147,7 +147,7 @@ always @(posedge i_clk) begin
     end 
 
 `ifdef SIM
-    if (cycle_ctr == 91) begin
+    if (cycle_ctr == 110) begin
         bus_halt <= 1'b1;
         $display("BUS      %0d: [%d] enough cycles for now", phase, cycle_ctr);
     end

saturn_bus_controller.v

@@ -89,6 +89,7 @@ saturn_control_unit control_unit (
     .o_dbg_reg_nibble  (ctrl_reg_nibble),
     .i_dbg_rstk_ptr    (dbg_rstk_ptr),
     .o_dbg_rstk_val    (ctrl_rstk_val),
+    .o_reg_rstk_ptr    (ctrl_reg_rstk_ptr),
 
     .o_alu_reg_dest    (dec_alu_reg_dest),
     .o_alu_reg_src_1   (dec_alu_reg_src_1),
@@ -114,6 +115,7 @@ wire [3:0]  ctrl_reg_p;
 
 wire [3:0]  ctrl_reg_nibble;
 wire [19:0] ctrl_rstk_val;
+wire [2:0]  ctrl_reg_rstk_ptr;
 
 wire [4:0]  dec_alu_reg_dest;
 wire [4:0]  dec_alu_reg_src_1;
@@ -152,6 +154,7 @@ saturn_debugger debugger (
     .i_dbg_reg_nibble  (ctrl_reg_nibble),
     .o_dbg_rstk_ptr    (dbg_rstk_ptr),
     .i_dbg_rstk_val    (ctrl_rstk_val),
+    .i_reg_rstk_ptr    (ctrl_reg_rstk_ptr),
 
     .i_alu_reg_dest    (dec_alu_reg_dest),
     .i_alu_reg_src_1   (dec_alu_reg_src_1),

saturn_control_unit.v

@@ -55,6 +55,7 @@ module saturn_control_unit (
     o_dbg_reg_nibble,
     i_dbg_rstk_ptr,
     o_dbg_rstk_val,
+    o_reg_rstk_ptr,
 
     o_alu_reg_dest,
     o_alu_reg_src_1,
@@ -99,6 +100,7 @@ input  wire [3:0]  i_dbg_reg_ptr;
 output reg  [3:0]  o_dbg_reg_nibble;
 input  wire [2:0]  i_dbg_rstk_ptr;
 output wire [19:0] o_dbg_rstk_val;
+output wire [2:0]  o_reg_rstk_ptr;
  
 output wire [4:0]  o_alu_reg_dest;
 output wire [4:0]  o_alu_reg_src_1;
@@ -237,7 +239,8 @@ saturn_regs_pc_rstk regs_pc_rstk (
     .o_reload_pc        (reload_PC),
 
     .i_dbg_rstk_ptr     (i_dbg_rstk_ptr),
-    .o_dbg_rstk_val     (o_dbg_rstk_val)
+    .o_dbg_rstk_val     (o_dbg_rstk_val),
+    .o_reg_rstk_ptr     (o_reg_rstk_ptr)
 );
 
 /**************************************************************************************************
@@ -307,7 +310,7 @@ always @(posedge i_clk) begin
 
     if (just_reset || (init_counter != 0)) begin
         $display("CTRL     %0d: [%d] initializing registers %0d", i_phase, i_cycle_ctr, init_counter);
-        reg_C[init_counter] <= 4'b0;
+        reg_C[init_counter] <= 4'h0;
         init_counter <= init_counter + 4'b1;
     end
 
@@ -442,6 +445,18 @@ always @(posedge i_clk) begin
                         reg_alu_mode <= dec_alu_imm_value[0];
                     end
                 `INSTR_TYPE_JUMP: begin end
+                `INSTR_TYPE_LOAD: 
+                    begin
+                        case (dec_alu_reg_dest)
+                            `ALU_REG_A: begin end
+                            `ALU_REG_C: 
+                                begin
+                                    $display("CTRL     %0d: [%d] C[%2d] <= %h", i_phase, i_cycle_ctr, dec_alu_ptr_begin, dec_alu_imm_value);
+                                    reg_C[dec_alu_ptr_begin] <= dec_alu_imm_value;
+                                end
+                            default:    $display("CTRL     %0d: [%d] unsupported register for load %0d", i_phase, i_cycle_ctr, dec_alu_reg_dest);
+                        endcase
+                    end
                 `INSTR_TYPE_RESET:
                     begin
                         $display("CTRL     %0d: [%d] exec : RESET", i_phase, i_cycle_ctr);

saturn_debugger.v

@@ -45,6 +45,7 @@ module saturn_debugger (
     i_dbg_reg_nibble,
     o_dbg_rstk_ptr,
     i_dbg_rstk_val,
+    i_reg_rstk_ptr,
 
     i_alu_reg_dest,
     i_alu_reg_src_1,
@@ -81,6 +82,7 @@ assign o_dbg_reg_ptr = registers_reg_ptr[3:0];
 input  wire [3:0]  i_dbg_reg_nibble;
 output reg  [2:0]  o_dbg_rstk_ptr;
 input  wire [19:0] i_dbg_rstk_val;
+input  wire [2:0]  i_reg_rstk_ptr;
 
 input  wire [4:0]  i_alu_reg_dest;
 input  wire [4:0]  i_alu_reg_src_1;
@@ -252,7 +254,7 @@ always @(posedge i_clk) begin
                         6'd1: registers_str[registers_ctr] <= "p";
                         6'd2: registers_str[registers_ctr] <= ":";
                         6'd3: registers_str[registers_ctr] <= " ";
-                        6'd4: registers_str[registers_ctr] <= "?";
+                        6'd4: registers_str[registers_ctr] <= hex[{1'b0, i_reg_rstk_ptr}];
                         6'd5: registers_str[registers_ctr] <= " ";
                         6'd6: registers_str[registers_ctr] <= " ";
                         6'd7: registers_str[registers_ctr] <= " ";
@@ -387,13 +389,13 @@ always @(posedge i_clk) begin
                     registers_reg_ptr <= registers_reg_ptr + 6'd1;
                     if (registers_reg_ptr == 6'd6) begin
                         registers_reg_ptr <= 6'd4;
+                        o_dbg_rstk_ptr  <= 3'd6;
                         registers_state <= `DBG_REG_RSTK6_VALUE;
                     end
                 end
             `DBG_REG_RSTK6_VALUE:
                 begin
-                    registers_str[registers_ctr] <= "?";
+                    registers_str[registers_ctr] <= hex[i_dbg_rstk_val[(registers_reg_ptr)*4+:4]];
-                    // registers_str[registers_ctr] <= hex[i_current_pc[(registers_reg_ptr)*4+:4]];
                     registers_reg_ptr <= registers_reg_ptr - 6'd1;
                     if (registers_reg_ptr == 6'd0) begin
                         registers_reg_ptr <= 6'd0;

saturn_def_alu.v

@@ -101,7 +101,8 @@
 `define INSTR_TYPE_ALU          1
 `define INSTR_TYPE_SET_MODE     2
 `define INSTR_TYPE_JUMP         3
-`define INSTR_TYPE_RESET        4
+`define INSTR_TYPE_LOAD         4
+`define INSTR_TYPE_RESET        5
 
 `define INSTR_TYPE_NONE         15
 

saturn_inst_decoder.v

@@ -125,6 +125,7 @@ reg [0:0] decode_started;
 
 reg [0:0] block_0x;
 reg [0:0] block_2x;
+reg [0:0] block_3x;
 reg [0:0] block_6x;
 reg [0:0] block_8x;
 reg [0:0] block_80x;
@@ -133,11 +134,14 @@ reg [0:0] block_82x;
 reg [0:0] block_84x_85x;
 
 reg [0:0] block_JUMP;
+reg [0:0] block_LOAD;
 
 /*
  * temporary variables
  */
 reg [2:0] jump_counter;
+reg [3:0] load_counter;
+reg [3:0] load_count;
 
 /*
  * initialization
@@ -166,6 +170,7 @@ initial begin
 
     block_0x        = 1'b0;
     block_2x        = 1'b0;
+    block_3x        = 1'b0;
     block_6x        = 1'b0;
     block_8x        = 1'b0;
     block_80x       = 1'b0;
@@ -174,9 +179,12 @@ initial begin
     block_84x_85x   = 1'b0;
 
     block_JUMP      = 1'b0;
+    block_LOAD      = 1'b0;
 
     /* local variables */
     jump_counter    = 3'd0;
+    load_counter    = 4'd0;
+    load_count      = 4'd0;
 
     /* last line of defense */
     o_decoder_error = 1'b0;
@@ -217,6 +225,7 @@ always @(posedge i_clk) begin
             case (i_nibble)
                 4'h0: block_0x <= 1'b1;
                 4'h2: block_2x <= 1'b1;
+                4'h3: block_3x <= 1'b1;
                 4'h6: 
                     begin
                         o_instr_type    <= `INSTR_TYPE_JUMP;
@@ -269,6 +278,18 @@ always @(posedge i_clk) begin
                 decode_started  <= 1'b0;
             end
 
+            if (block_3x) begin
+                $display("DECODER  %0d: [%d] LC %h", i_phase, i_cycle_ctr, i_nibble);
+                o_alu_reg_dest  <= `ALU_REG_C;
+                o_alu_ptr_begin <= i_reg_p;
+                o_alu_ptr_end   <= (i_reg_p + i_nibble) & 4'hF;
+                load_counter    <= 4'h0;
+                load_count      <= i_nibble;
+                o_instr_execute <= 1'b1;
+                block_LOAD      <= 1'b1;
+                block_3x        <= 1'b0;
+            end
+
             if (block_6x) begin
                 // $display("DECODER  %0d: [%d] GOTO %h", i_phase, i_cycle_ctr, i_nibble);
                 jump_counter <= jump_counter + 3'd1;
@@ -389,6 +410,23 @@ always @(posedge i_clk) begin
                 end
             end
 
+            if (block_LOAD) begin
+                o_instr_type    <= `INSTR_TYPE_LOAD;
+                o_alu_imm_value <= i_nibble;
+                load_counter    <= load_counter + 4'd1;
+                if (load_counter == load_count) begin
+                    block_LOAD <= 1'b0;
+                    o_instr_decoded <= 1'b1;
+                    decode_started  <= 1'b0;
+                end
+            end
+
+        end
+
+        /* need to increment this at the same time the pointer is used */
+        if (i_phases[3] && block_LOAD && (o_instr_type == `INSTR_TYPE_LOAD)) begin
+            $display("DECODER  %0d: [%d] load ptr_begin <= %0d", i_phase, i_cycle_ctr, (o_alu_ptr_begin + 4'd1) & 4'hF);
+            o_alu_ptr_begin <= (o_alu_ptr_begin + 4'd1) & 4'hF;
         end
 
         /* decoder cleanup only after the instruction is completely decoded and execution has started */
@@ -427,6 +465,7 @@ always @(posedge i_clk) begin
 
         block_0x        <= 1'b0;
         block_2x        <= 1'b0;
+        block_3x        <= 1'b0;
         block_6x        <= 1'b0;
         block_8x        <= 1'b0;
         block_80x       <= 1'b0;
@@ -435,9 +474,12 @@ always @(posedge i_clk) begin
         block_84x_85x   <= 1'b0;
 
         block_JUMP      <= 1'b0;
+        block_LOAD      <= 1'b0;
 
         /* local variables */
         jump_counter    = 3'd0;
+        load_counter    = 4'd0;
+        load_count      = 4'd0;
 
         /* invalid instruction */
         o_decoder_error = 1'b0;

saturn_regs_pc_rstk.v

@@ -40,7 +40,8 @@ module saturn_regs_pc_rstk (
 
     /* debugger access */
     i_dbg_rstk_ptr,
-    o_dbg_rstk_val
+    o_dbg_rstk_val,
+    o_reg_rstk_ptr
 );
 
 input  wire [0:0]  i_clk;
@@ -62,8 +63,10 @@ output reg  [0:0]  o_reload_pc;
 
 input  wire [2:0]  i_dbg_rstk_ptr;
 output wire [19:0] o_dbg_rstk_val;
+output wire [2:0]  o_reg_rstk_ptr;
 
 assign o_dbg_rstk_val = reg_RSTK[i_dbg_rstk_ptr];
+assign o_reg_rstk_ptr     = reg_rstk_ptr;
 
 /**************************************************************************************************
  *
@@ -184,7 +187,7 @@ always @(posedge i_clk) begin
             $write("PC_RSTK  %0d: [%d] execute jump %0d", i_phase, i_cycle_ctr, i_jump_length);
             if (i_push_pc) begin
                 $write(" ( push %5h => RSTK[%0d])", reg_PC, reg_rstk_ptr + 3'd1);
-                reg_RSTK[reg_rstk_ptr + 3'd1] <= reg_PC;
+                reg_RSTK[(reg_rstk_ptr + 3'o1)&3'o7] <= reg_PC;
                 reg_rstk_ptr <= reg_rstk_ptr + 3'd1;
             end
             $display("");
@@ -195,12 +198,12 @@ always @(posedge i_clk) begin
 
     end
 
-    if (i_phases[0] && i_clk_en) begin
+    // if (i_phases[0] && i_clk_en) begin
-        $write("RSTK : ptr %0d | ", reg_rstk_ptr);
+    //     $write("RSTK : ptr %0d | ", reg_rstk_ptr);
-        for (tmp_ctr = 4'd0; tmp_ctr < 4'd8; tmp_ctr = tmp_ctr + 4'd1)
+    //     for (tmp_ctr = 4'd0; tmp_ctr < 4'd8; tmp_ctr = tmp_ctr + 4'd1)
-            $write("%0d => %5h | ", tmp_ctr, reg_RSTK[tmp_ctr]);
+    //         $write("%0d => %5h | ", tmp_ctr, reg_RSTK[tmp_ctr]);
-        $write("\n");
+    //     $write("\n");
-    end
+    // end
 
     if (i_reset) begin
         o_reload_pc  <= 1'b0;