tested all the way to cycle 400 where transfers from memory need to be fixed in the bus controller

history.txt

@@ -37,3 +37,4 @@ second delay is posedge $glbnet$clk -> <async>
 2019-02-17 12:58    1679         68.43MHz   38.91ns     12.77ns     10906    70.19MHz   18.76ns     4.00ns
 2019-02-17 15:11    1677         70.29MHz   34.92ns     13.01ns     11788    74.69MHz   17.42ns     3.88ns
 2019-02-17 19:30    1637         74.68MHz   34.80ns     12.77ns     11687    68.49Mhz   18.03ns     4.01ns
+2019-02-17 20:25    1733         72.37MHz   32.87ns     12.77ns     12213    73.52MHz   16.22ns     3.87ns

saturn_bus_ctrl.v

@@ -89,10 +89,12 @@ reg  [0:0] cmd_load_dp_s;
 reg  [0:0] cmd_config_s;
 reg  [0:0] cmd_reset_s;
 
-wire [0:0] do_pc_read;
+wire [0:0] do_cmd_pc_read;
+wire [0:0] do_display_stalled;
 
 wire [0:0] do_cmd_load_dp;
 wire [0:0] do_cmd_dp_write;
+wire [0:0] do_dp_write_data;
 wire [0:0] do_pc_read_after_dp_write;
 wire [0:0] cmd_load_dp_dp_write_uc;
 
@@ -110,6 +112,7 @@ wire [0:0] do_unstall;
 
 assign do_cmd_load_dp            = i_cmd_load_dp && !cmd_load_dp_s;
 assign do_cmd_dp_write           = i_cmd_dp_write && cmd_load_dp_s && addr_s && !cmd_dp_write_s;
+assign do_dp_write_data          = i_cmd_dp_write && cmd_load_dp_s && addr_s && cmd_dp_write_s;
 assign do_pc_read_after_dp_write = !i_cmd_dp_write && cmd_load_dp_s && cmd_dp_write_s;
 assign cmd_load_dp_dp_write_uc   = cmd_load_dp_s && cmd_dp_write_s && cmd_pc_read_s;
 
@@ -123,11 +126,17 @@ assign do_pc_read_after_reset    = i_cmd_reset && cmd_reset_s;
 assign cmd_reset_sc              = !o_stalled_by_bus && i_cmd_reset && !cmd_reset_s;
 assign cmd_reset_uc              = cmd_reset_s && cmd_pc_read_s;
 
-assign do_pc_read                = !cmd_pc_read_s && 
+assign do_cmd_pc_read            = !cmd_pc_read_s && 
                                    (do_pc_read_after_dp_write ||
                                     do_pc_read_after_config || 
                                     do_pc_read_after_reset);
 
+assign do_display_stalled        = i_read_stall && !o_stalled_by_bus &&
+                                   !(do_cmd_pc_read ||
+                                     do_cmd_dp_write ||
+                                     do_dp_write_data ||
+                                     do_pc_read_after_dp_write);
+
 assign do_unstall                = cmd_load_dp_dp_write_uc ||
                                    cmd_config_uc ||
                                    cmd_reset_uc;
@@ -209,7 +218,7 @@ always @(posedge i_clk) begin
      * after a data transfer
      */
 
-    if (do_pc_read) begin
+    if (do_cmd_pc_read) begin
       $display("BUS_SEND %0d: [%d] PC_READ", `PH_BUS_SEND, i_cycle_ctr);
       o_bus_data    <= `BUSCMD_PC_READ;
       last_cmd      <= `BUSCMD_PC_READ;
@@ -286,7 +295,7 @@ always @(posedge i_clk) begin
      * send DP_WRITE first if necessary
      */
 
-    if (i_cmd_dp_write && (addr_cnt == 5)) begin
+    if (do_dp_write_data) begin
       if (last_cmd != `BUSCMD_DP_WRITE) begin
       end else begin
         $display("BUS_SEND %0d: [%d] WRITE %h =>", `PH_BUS_SEND, i_cycle_ctr, i_nibble);
@@ -314,18 +323,10 @@ always @(posedge i_clk) begin
           local_pc <= local_pc + 1;
       end 
       endcase
-    // else    
+    
-    //   if (!o_stalled_by_bus) begin
+    if (do_display_stalled) begin
-    //     $write("BUS_RECV %0d: [%d] STALLED (last ", `PH_BUS_RECV, i_cycle_ctr);  
+      $display("BUS_RECV %0d: [%d] STALLED", `PH_BUS_RECV, i_cycle_ctr);
-    //     case (last_cmd)
+    end
-    //       `BUSCMD_PC_READ: $write("PC_READ");
-    //       `BUSCMD_DP_READ: $write("DP_READ");
-    //       `BUSCMD_DP_WRITE: $write("DP_WRITE");
-    //       `BUSCMD_RESET:   $write("RESET");
-    //       default: $write("%h", last_cmd);
-    //     endcase
-    //     $display(")");
-    //   end 
 
   /*
    *

saturn_core.v

@@ -358,7 +358,7 @@ always @(posedge clk) begin
 
 		clock_end	    <= 0;
 		cycle_ctr	    <= ~0;
-		max_cycle     <= 170;
+		max_cycle     <= 405;
 
 		mem_ctrl_stall <= 0;
 `ifndef SIM

saturn_decoder.v

@@ -528,7 +528,6 @@ always @(posedge i_clk) begin
 `ifdef SIM
     $display("block_15xx %h", i_nibble);
 `endif
-    o_alu_debug   <= 1;
     o_ins_alu_op  <= 1;
     o_ins_decoded <= 1;
     next_nibble   <= 0;
@@ -602,7 +601,6 @@ always @(posedge i_clk) begin
     o_alu_op        <= (i_nibble[3] && i_nibble[2])?`ALU_OP_DEC:`ALU_OP_ADD;
     next_nibble     <= 0;
     o_ins_decoded   <= 1;
-    o_alu_debug <= 1;
 `ifdef SIM
     // o_unimplemented <= 0;
 `endif