2019-02-07 06:29:47 +01:00
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`include "bus_commands.v"
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`ifndef _HP48_IO_RAM
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`define _HP48_IO_RAM
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/**************************************************************************************************
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*
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* I/O ram
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* length: 64 nibbles
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*
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*
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*/
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module hp48_io_ram (
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2019-02-07 22:54:06 +01:00
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input strobe,
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2019-02-07 06:29:47 +01:00
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input reset,
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input [19:0] address,
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input [3:0] command,
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input [3:0] nibble_in,
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output reg [3:0] nibble_out,
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2019-02-09 09:32:29 +01:00
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output active,
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2019-02-08 21:11:47 +01:00
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input daisy_in,
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output daisy_out,
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output reg error
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2019-02-07 06:29:47 +01:00
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);
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localparam IO_RAM_LEN = 64;
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// localparam BUSCMD_DP_WRITE = C_BUSCMD_DP_WRITE;
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// localparam BUSCMD_CONFIGURE = C_BUSCMD_CONFIGURE;
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reg [0:0] configured;
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reg [19:0] base_addr;
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reg [19:0] pc_ptr;
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2019-02-08 21:11:47 +01:00
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reg [19:0] dp_ptr;
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reg [3:0] mmio_ram [0:IO_RAM_LEN-1];
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assign daisy_out = configured;
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2019-02-07 06:29:47 +01:00
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/*
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*
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*
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*/
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initial
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begin
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`ifdef SIM
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$display("io_ram: set unconfigured");
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`endif
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configured = 0;
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`ifdef SIM
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$display("io_ram: reset error flag");
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`endif
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2019-02-08 21:11:47 +01:00
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error = 1'b0;
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2019-02-07 06:29:47 +01:00
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`ifdef SIM
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$display("io_ram: setting data pointer to 0");
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`endif
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2019-02-08 21:11:47 +01:00
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dp_ptr = 0;
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2019-02-07 06:29:47 +01:00
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`ifdef SIM
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2019-02-09 00:55:09 +01:00
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// initialization only for simulation
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2019-02-07 06:29:47 +01:00
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$display("io_ram: initializing to 0");
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for (base_addr = 0; base_addr < IO_RAM_LEN; base_addr++)
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begin
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$write(".");
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2019-02-09 01:13:57 +01:00
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mmio_ram[base_addr] = 0;
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2019-02-07 06:29:47 +01:00
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end
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2019-02-08 21:11:47 +01:00
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$display("io_ram: setting base address to 0");
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`endif
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base_addr = 0;
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2019-02-07 06:29:47 +01:00
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`ifdef SIM
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$write("\n");
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$display("io_ram: initialized");
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`endif
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2019-02-09 09:32:29 +01:00
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// $monitor("MMIO MON | PC %h | DP %h | P %h | A %h | B %h | L %h | CNF %b | RD %b | WR %b | ACT %b",
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// pc_ptr, dp_ptr, ptr_value, access_addr, base_addr, last_addr,
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// configured, can_read, can_write, active);
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2019-02-07 06:29:47 +01:00
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end
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/*
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*
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*
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*/
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2019-02-09 01:13:57 +01:00
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wire cmd_bus_pc;
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wire cmd_bus_dp;
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wire cmd_read;
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wire cmd_write;
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assign cmd_bus_pc = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_PC_WRITE);
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assign cmd_bus_dp = (command == `BUSCMD_DP_READ) | (command == `BUSCMD_DP_WRITE);
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2019-02-09 09:32:29 +01:00
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assign cmd_read = (command == `BUSCMD_PC_READ) | (command == `BUSCMD_DP_READ);
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assign cmd_write = (command == `BUSCMD_PC_WRITE) | (command == `BUSCMD_DP_WRITE);
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2019-02-07 06:29:47 +01:00
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2019-02-09 09:32:29 +01:00
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wire [19:0] last_addr;
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2019-02-08 21:11:47 +01:00
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2019-02-09 09:32:29 +01:00
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assign last_addr = base_addr + IO_RAM_LEN - 1;
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wire pc_lower;
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wire pc_higher;
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wire use_pc;
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wire dp_lower;
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wire dp_higher;
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wire use_dp;
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assign pc_lower = pc_ptr < base_addr;
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assign pc_higher = pc_ptr > last_addr;
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assign use_pc = !(pc_lower | pc_higher);
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assign dp_lower = dp_ptr < base_addr;
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assign dp_higher = dp_ptr > last_addr;
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assign use_dp = !(dp_lower | dp_higher);
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wire [19:0] ptr_value;
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wire [19:0] access_addr;
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assign ptr_value = (cmd_bus_dp?dp_ptr:pc_ptr);
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assign access_addr = ptr_value - base_addr;
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wire read_pc;
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wire write_pc;
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wire read_dp;
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wire write_dp;
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2019-02-07 06:29:47 +01:00
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2019-02-09 09:32:29 +01:00
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assign read_pc = use_pc & cmd_bus_pc & cmd_read;
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assign write_pc = use_pc & cmd_bus_pc & cmd_write;
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assign read_dp = use_dp & cmd_bus_dp & cmd_read;
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assign write_dp = use_dp & cmd_bus_dp & cmd_write;
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wire can_read;
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wire can_write;
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assign can_read = configured & (read_pc | read_dp);
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assign can_write = configured & (write_pc | write_dp);
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assign active = can_read | can_write;
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2019-02-09 01:13:57 +01:00
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always @(posedge strobe) begin
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// read from ram
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2019-02-09 09:32:29 +01:00
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if (can_read) begin
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nibble_out = mmio_ram[access_addr];
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end
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2019-02-09 01:13:57 +01:00
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end
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always @(posedge strobe) begin
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// write to ram
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2019-02-09 09:32:29 +01:00
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if (can_write) begin
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mmio_ram[access_addr] <= nibble_in;
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end
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2019-02-09 01:13:57 +01:00
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end
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2019-02-08 21:11:47 +01:00
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always @(posedge strobe) begin
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case (command)
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`BUSCMD_PC_READ: begin
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pc_ptr <= pc_ptr + 1;
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2019-02-09 09:32:29 +01:00
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$display("MMIO (%b - %5h) ACT %b - %s_PC %5h (%5h) -> %h",
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configured, base_addr, active,
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cmd_read?"READ":"WRITE", ptr_value, access_addr,
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cmd_read?nibble_out:nibble_in);
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2019-02-08 21:11:47 +01:00
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end
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2019-02-09 01:13:57 +01:00
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`BUSCMD_DP_READ, `BUSCMD_DP_WRITE: begin
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2019-02-08 21:11:47 +01:00
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dp_ptr <= dp_ptr + 1;
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2019-02-09 09:32:29 +01:00
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$display("MMIO (%b - %5h) ACT %b - %s_DP %5h (%5h) -> %h",
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configured, base_addr, active,
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cmd_read?"READ":"WRITE", ptr_value, access_addr,
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cmd_read?nibble_out:nibble_in);
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2019-02-08 21:11:47 +01:00
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end
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`BUSCMD_LOAD_PC: begin
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// $display("MMIO (%b - %5h) - LOAD_PC %5h", configured, base_addr, address);
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pc_ptr <= address;
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end
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`BUSCMD_LOAD_DP: begin
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dp_ptr <= address;
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// $display("MMIO (%b - %5h) - LOAD_DP %5h", configured, base_addr, address);
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end
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`BUSCMD_CONFIGURE: begin
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if (!configured) begin
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2019-02-09 00:02:09 +01:00
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if (daisy_in) begin
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base_addr <= address;
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configured <= 1;
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// $display("MMIO (%b - %5h) - CONFIGURE %5h", configured, base_addr, address);
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end else begin
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$display("MMIO (%b - %5h) - CAN'T CONFIGURE - DAISY_IN NOT SET %5h", configured, base_addr, address);
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end
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2019-02-08 21:11:47 +01:00
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end else begin
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2019-02-09 00:02:09 +01:00
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// $display("MMIO (%b - %5h) - ALREADY CONFIGURED %5h", configured, base_addr, address);
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2019-02-08 21:11:47 +01:00
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end
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end
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2019-02-09 00:02:09 +01:00
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`BUSCMD_RESET: begin
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base_addr <= 0;
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configured <= 0;
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$display("MMIO (%b - %5h) - RESET", configured, base_addr);
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end
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2019-02-08 21:11:47 +01:00
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default: begin
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$display("MMIO (%b - %5h) - UNIMPLEMENTED COMMAND %d %5h", configured, base_addr, command, address);
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error <= 1;
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end
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endcase
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end
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2019-02-07 06:29:47 +01:00
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endmodule
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`endif
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