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Standardize formatting again
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1e0dc878dd
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7 changed files with 2 additions and 12 deletions
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@ -158,8 +158,6 @@ module GBA
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when 0x88 then @soundbias.value.to_u8!
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when 0x88 then @soundbias.value.to_u8!
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when 0x89 then (@soundbias.value >> 8).to_u8!
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when 0x89 then (@soundbias.value >> 8).to_u8!
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else puts "Unmapped APU read ~ addr:#{hex_str io_addr.to_u8}".colorize.fore(:red); 0_u8 # todo: open bus
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else puts "Unmapped APU read ~ addr:#{hex_str io_addr.to_u8}".colorize.fore(:red); 0_u8 # todo: open bus
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end
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end
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end
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end
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@ -85,8 +85,6 @@ module GBA
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when 0x64 then 0xFF_u8 # write-only
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when 0x64 then 0xFF_u8 # write-only
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when 0x65 then 0xBF_u8 | (@length_enable ? 0x40 : 0)
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when 0x65 then 0xBF_u8 | (@length_enable ? 0x40 : 0)
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else puts "Reading from invalid Channel1 register: #{hex_str index.to_u16}".colorize.fore(:red); 0_u8 # todo: open bus
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else puts "Reading from invalid Channel1 register: #{hex_str index.to_u16}".colorize.fore(:red); 0_u8 # todo: open bus
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end
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end
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end
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end
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@ -50,8 +50,6 @@ module GBA
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when 0x6C then 0xFF_u8 # write-only
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when 0x6C then 0xFF_u8 # write-only
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when 0x6D then 0xBF_u8 | (@length_enable ? 0x40 : 0)
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when 0x6D then 0xBF_u8 | (@length_enable ? 0x40 : 0)
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else puts "Reading from invalid Channel2 register: #{hex_str index.to_u16}".colorize.fore(:red); 0_u8 # todo: open bus
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else puts "Reading from invalid Channel2 register: #{hex_str index.to_u16}".colorize.fore(:red); 0_u8 # todo: open bus
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end
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end
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end
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end
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@ -63,8 +63,6 @@ module GBA
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@wave_ram[@wave_ram_bank][index - WAVE_RAM_RANGE.begin]
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@wave_ram[@wave_ram_bank][index - WAVE_RAM_RANGE.begin]
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end
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end
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else puts "Reading from invalid Channel3 register: #{hex_str index.to_u16}".colorize.fore(:red); 0_u8 # todo: open bus
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else puts "Reading from invalid Channel3 register: #{hex_str index.to_u16}".colorize.fore(:red); 0_u8 # todo: open bus
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end.to_u8
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end.to_u8
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end
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end
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@ -50,8 +50,6 @@ module GBA
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when 0x7C then @clock_shift << 4 | @width_mode << 3 | @divisor_code
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when 0x7C then @clock_shift << 4 | @width_mode << 3 | @divisor_code
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when 0x7D then 0xBF | (@length_enable ? 0x40 : 0)
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when 0x7D then 0xBF | (@length_enable ? 0x40 : 0)
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else puts "Reading from invalid Channel4 register: #{hex_str index.to_u16}".colorize.fore(:red); 0_u8 # todo: open bus
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else puts "Reading from invalid Channel4 register: #{hex_str index.to_u16}".colorize.fore(:red); 0_u8 # todo: open bus
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end.to_u8
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end.to_u8
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end
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end
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@ -7,7 +7,7 @@ module GBA
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address = @r[rb]
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address = @r[rb]
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unless list == 0
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unless list == 0
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final_addr = 4_u32 * list.popcount + address
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final_addr = 4_u32 * list.popcount + address
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if load # ldmia
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if load # ldmia
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@r[rb] = final_addr # thumb ldmia writes back immediately
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@r[rb] = final_addr # thumb ldmia writes back immediately
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8.times do |idx|
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8.times do |idx|
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if bit?(list, idx)
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if bit?(list, idx)
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@ -4,7 +4,7 @@ module GBA
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alias Word = UInt32
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alias Word = UInt32
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alias Words = Slice(UInt32)
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alias Words = Slice(UInt32)
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record BGR16, value : UInt16 do # xBBBBBGGGGGRRRRR
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record BGR16, value : UInt16 do # xBBBBBGGGGGRRRRR
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# Create a new BGR16 struct with the given values. Trucates at 5 bits.
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# Create a new BGR16 struct with the given values. Trucates at 5 bits.
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def initialize(blue : Number, green : Number, red : Number)
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def initialize(blue : Number, green : Number, red : Number)
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@value = (blue <= 0x1F ? blue.to_u16 : 0x1F_u16) << 10 |
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@value = (blue <= 0x1F ? blue.to_u16 : 0x1F_u16) << 10 |
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(green <= 0x1F ? green.to_u16 : 0x1F_u16) << 5 |
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(green <= 0x1F ? green.to_u16 : 0x1F_u16) << 5 |
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