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DRAMSim2.info | ||
DRAMSim2.SlackBuild | ||
README | ||
slack-desc |
DRAMSim2 is a cycle accurate model of a DRAM memory controller, the DRAM modules which comprise system storage, and the bus by which they communicate. All major components in a modern memory system are modeled as their own respective objects within the source, including: ranks, banks, command queue, the memory controller, etc. For setting the DEBUG mode use the enviroment variable DEBUG=1