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3 commits

Author SHA1 Message Date
Gwenhael Le Moine
fa1412a6c8
style 2024-10-13 14:22:34 +02:00
Gwenhael Le Moine
47027c375f
split-out inner switch from ExecGroup_1 2024-10-13 14:13:28 +02:00
Gwenhael Le Moine
5f90d54c5e
print --help on stdout 2024-10-13 14:12:31 +02:00
3 changed files with 252 additions and 249 deletions

137
src/cpu.c
View file

@ -1563,43 +1563,10 @@ static void ExecGroup_0( void )
} }
} }
/* Instruction Group_1 */ /* Instruction Group_13 */
static void ExecGroup_1( void ) static void ExecGroup_13( void )
{ {
Nibble n = FetchNibble( cpu_status.PC++ );
Nibble f;
int rn, ac;
int oc, is;
Address ta; Address ta;
debug1( CPU_CHF_MODULE_ID, DEBUG_C_TRACE, CPU_I_CALLED, "ExecGroup_1" );
switch ( n ) {
case 0: /* Rn=A/C */
n = FetchNibble( cpu_status.PC++ );
rn = GET_Rn( n );
ac = GET_AC( n );
CopyRR( cpu_status.R[ rn ], ( ac ? cpu_status.C : cpu_status.A ), FS_W );
break;
case 1: /* A/C=Rn */
n = FetchNibble( cpu_status.PC++ );
rn = GET_Rn( n );
ac = GET_AC( n );
CopyRR( ( ac ? cpu_status.C : cpu_status.A ), cpu_status.R[ rn ], FS_W );
break;
case 2:
/* ARnEX, CRnEX */
n = FetchNibble( cpu_status.PC++ );
rn = GET_Rn( n );
ac = GET_AC( n );
ExchRR( ( ac ? cpu_status.C : cpu_status.A ), cpu_status.R[ rn ], FS_W );
break;
case 3:
/* Copy/Exchange A/C and D0/D1 */ /* Copy/Exchange A/C and D0/D1 */
switch ( FetchNibble( cpu_status.PC++ ) ) { switch ( FetchNibble( cpu_status.PC++ ) ) {
case 0: /* D0=A */ case 0: /* D0=A */
@ -1682,9 +1649,11 @@ static void ExecGroup_1( void )
Addr2RS( cpu_status.C, ta ); Addr2RS( cpu_status.C, ta );
break; break;
} }
break; }
case 4: /* Instruction Group_14 */
static void ExecGroup_14( void )
{
/* Load/Store A/C to @D0/@D1, Field selector A or B */ /* Load/Store A/C to @D0/@D1, Field selector A or B */
switch ( FetchNibble( cpu_status.PC++ ) ) { switch ( FetchNibble( cpu_status.PC++ ) ) {
case 0: /* DAT0=A A */ case 0: /* DAT0=A A */
@ -1751,14 +1720,16 @@ static void ExecGroup_1( void )
ReadDAT( cpu_status.C, cpu_status.D1, FS_B ); ReadDAT( cpu_status.C, cpu_status.D1, FS_B );
break; break;
} }
break; }
case 5: /* Instruction Group_15 */
static void ExecGroup_15( void )
{
/* Load/Store A/C to @D0/@D1, Other Field Selectors */ /* Load/Store A/C to @D0/@D1, Other Field Selectors */
n = FetchNibble( cpu_status.PC++ ); Nibble n = FetchNibble( cpu_status.PC++ );
f = FetchNibble( cpu_status.PC++ ); Nibble f = FetchNibble( cpu_status.PC++ );
oc = GET_OC_3b( n ); int oc = GET_OC_3b( n );
is = GET_IMMEDIATE_FS_FLAG( n ); int is = GET_IMMEDIATE_FS_FLAG( n );
switch ( oc ) { switch ( oc ) {
case 0: /* DAT0=A */ case 0: /* DAT0=A */
@ -1822,67 +1793,102 @@ static void ExecGroup_1( void )
ChfSignal( CPU_CHF_MODULE_ID ); ChfSignal( CPU_CHF_MODULE_ID );
break; break;
} }
}
/* Instruction Group_1 */
static void ExecGroup_1( void )
{
Nibble n = FetchNibble( cpu_status.PC++ );
int rn, ac;
Address ta;
debug1( CPU_CHF_MODULE_ID, DEBUG_C_TRACE, CPU_I_CALLED, "ExecGroup_1" );
switch ( n ) {
case 0: /* Rn=A/C */
n = FetchNibble( cpu_status.PC++ );
rn = GET_Rn( n );
ac = GET_AC( n );
CopyRR( cpu_status.R[ rn ], ( ac ? cpu_status.C : cpu_status.A ), FS_W );
break; break;
case 6: case 1: /* A/C=Rn */
/* D0=D0+n+1 */ n = FetchNibble( cpu_status.PC++ );
rn = GET_Rn( n );
ac = GET_AC( n );
CopyRR( ( ac ? cpu_status.C : cpu_status.A ), cpu_status.R[ rn ], FS_W );
break;
case 2: /* ARnEX, CRnEX */
n = FetchNibble( cpu_status.PC++ );
rn = GET_Rn( n );
ac = GET_AC( n );
ExchRR( ( ac ? cpu_status.C : cpu_status.A ), cpu_status.R[ rn ], FS_W );
break;
case 3:
ExecGroup_13();
break;
case 4:
ExecGroup_14();
break;
case 5:
ExecGroup_15();
break;
case 6: /* D0=D0+n+1 */
n = FetchNibble( cpu_status.PC++ ); n = FetchNibble( cpu_status.PC++ );
ta = ( cpu_status.D0 + n + 1 ) & ADDRESS_MASK; ta = ( cpu_status.D0 + n + 1 ) & ADDRESS_MASK;
cpu_status.carry = ( ta < cpu_status.D0 ); cpu_status.carry = ( ta < cpu_status.D0 );
cpu_status.D0 = ta; cpu_status.D0 = ta;
break; break;
case 7: case 7: /* D1=D1+n+1 */
/* D1=D1+n+1 */
n = FetchNibble( cpu_status.PC++ ); n = FetchNibble( cpu_status.PC++ );
ta = ( cpu_status.D1 + n + 1 ) & ADDRESS_MASK; ta = ( cpu_status.D1 + n + 1 ) & ADDRESS_MASK;
cpu_status.carry = ( ta < cpu_status.D1 ); cpu_status.carry = ( ta < cpu_status.D1 );
cpu_status.D1 = ta; cpu_status.D1 = ta;
break; break;
case 8: case 8: /* D0=D0-(n+1) */
/* D0=D0-(n+1) */
n = FetchNibble( cpu_status.PC++ ); n = FetchNibble( cpu_status.PC++ );
ta = ( cpu_status.D0 - n - 1 ) & ADDRESS_MASK; ta = ( cpu_status.D0 - n - 1 ) & ADDRESS_MASK;
cpu_status.carry = ( ta > cpu_status.D0 ); cpu_status.carry = ( ta > cpu_status.D0 );
cpu_status.D0 = ta; cpu_status.D0 = ta;
break; break;
case 9: case 9: /* D0=(2) nn */
/* D0=(2) nn */
FetchD( &cpu_status.D0, 2 ); FetchD( &cpu_status.D0, 2 );
break; break;
case 0xA: case 0xA: /* D0=(4) nn */
/* D0=(4) nn */
FetchD( &cpu_status.D0, 4 ); FetchD( &cpu_status.D0, 4 );
break; break;
case 0xB: case 0xB: /* D0=(5) nn */
/* D0=(5) nn */
FetchD( &cpu_status.D0, 5 ); FetchD( &cpu_status.D0, 5 );
break; break;
case 0xC: case 0xC: /* D1=D1-(n+1) */
/* D1=D1-(n+1) */
n = FetchNibble( cpu_status.PC++ ); n = FetchNibble( cpu_status.PC++ );
ta = ( cpu_status.D1 - n - 1 ) & ADDRESS_MASK; ta = ( cpu_status.D1 - n - 1 ) & ADDRESS_MASK;
cpu_status.carry = ( ta > cpu_status.D1 ); cpu_status.carry = ( ta > cpu_status.D1 );
cpu_status.D1 = ta; cpu_status.D1 = ta;
break; break;
case 0xD: case 0xD: /* D1=(2) nn */
/* D1=(2) nn */
FetchD( &cpu_status.D1, 2 ); FetchD( &cpu_status.D1, 2 );
break; break;
case 0xE: case 0xE: /* D1=(4) nn */
/* D1=(4) nn */
FetchD( &cpu_status.D1, 4 ); FetchD( &cpu_status.D1, 4 );
break; break;
case 0xF: case 0xF: /* D1=(5) nn */
/* D1=(5) nn */
FetchD( &cpu_status.D1, 5 ); FetchD( &cpu_status.D1, 5 );
break; break;
@ -1997,12 +2003,13 @@ static void ExecGroup_808( void )
/* Instruction Group_80 */ /* Instruction Group_80 */
static void ExecGroup_80B( void ) static void ExecGroup_80B( void )
{ {
debug1( CPU_CHF_MODULE_ID, DEBUG_C_TRACE, CPU_I_CALLED, "ExecBUSCC" );
// FIXME: 49g bugs here on display change // FIXME: 49g bugs here on display change
// DEBUG_print_cpu_instruction(); // DEBUG_print_cpu_instruction();
ChfGenerate( CPU_CHF_MODULE_ID, __FILE__, __LINE__, CPU_F_INTERR, CHF_WARNING, "BUSCC" ); ChfGenerate( CPU_CHF_MODULE_ID, __FILE__, __LINE__, CPU_F_INTERR, CHF_WARNING, "BUSCC not implemented" );
ChfSignal( CPU_CHF_MODULE_ID ); ChfSignal( CPU_CHF_MODULE_ID );
debug1( CPU_CHF_MODULE_ID, DEBUG_C_TRACE, CPU_I_CALLED, "ExecGroup_80B" );
} }
/* Instruction Group_80 */ /* Instruction Group_80 */

View file

@ -161,9 +161,7 @@ static Address Get5NibblesAbs( Address pc )
*/ */
static Address DisHexConstant( Address start, char* ob, int m ) static Address DisHexConstant( Address start, char* ob, int m )
{ {
int i; for ( int i = 0; i < m; i++ )
for ( i = 0; i < m; i++ )
strcat( ob, hex_digit[ ( int )FetchNibble( start + m - i - 1 ) ] ); strcat( ob, hex_digit[ ( int )FetchNibble( start + m - i - 1 ) ] );
return start + m; return start + m;
@ -2213,14 +2211,12 @@ static Address DisGroup_8( Address pc, char* ob )
.- */ .- */
Address Disassemble( Address pc, char ob[ DISASSEMBLE_OB_SIZE ] ) Address Disassemble( Address pc, char ob[ DISASSEMBLE_OB_SIZE ] )
{ {
Nibble n;
/* Disassemble current program counter */ /* Disassemble current program counter */
sprintf( ob, "A_%05X\t", pc ); sprintf( ob, "A_%05X\t", pc );
ob += strlen( ob ); ob += strlen( ob );
/* Get first instruction nibble */ /* Get first instruction nibble */
n = FetchNibble( pc++ ); Nibble n = FetchNibble( pc++ );
switch ( n ) { switch ( n ) {
case 0: case 0:

View file

@ -328,7 +328,7 @@ config_t* config_init( int argc, char* argv[] )
switch ( c ) { switch ( c ) {
case 'h': case 'h':
fprintf( stderr, help_text, config.progname ); fprintf( stdout, help_text, config.progname );
exit( EXIT_SUCCESS ); exit( EXIT_SUCCESS );
break; break;
case 6110: case 6110: