1073 lines
42 KiB
C
1073 lines
42 KiB
C
#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sys/time.h>
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#include <unistd.h>
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#include "emulator.h"
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#include "emulator_inner.h"
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#include "romio.h"
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#include "config.h"
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#include "ui.h" /* ui_disp_draw_nibble(); ui_menu_draw_nibble(); */
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#define MCTL_MMIO_SX 0
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#define MCTL_SysRAM_SX 1
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#define MCTL_PORT1_SX 2
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#define MCTL_PORT2_SX 3
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#define MCTL_EXTRA_SX 4
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#define MCTL_SysROM_SX 5
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#define MCTL_MMIO_GX 0
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#define MCTL_SysRAM_GX 1
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#define MCTL_BANK_GX 2
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#define MCTL_PORT1_GX 3
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#define MCTL_PORT2_GX 4
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#define MCTL_SysROM_GX 5
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#define DISP_INSTR_OFF 0x10
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long nibble_masks[ 16 ] = { 0x0000000f, 0x000000f0, 0x00000f00, 0x0000f000, 0x000f0000, 0x00f00000, 0x0f000000, 0xf0000000,
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0x0000000f, 0x000000f0, 0x00000f00, 0x0000f000, 0x000f0000, 0x00f00000, 0x0f000000, 0xf0000000 };
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display_t display;
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void ( *write_nibble )( long addr, int val );
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int ( *read_nibble )( long addr );
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int ( *read_nibble_crc )( long addr );
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static int line_counter = -1;
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static inline int calc_crc( int nib )
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{
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saturn.crc = ( saturn.crc >> 4 ) ^ ( ( ( saturn.crc ^ nib ) & 0xf ) * 0x1081 );
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return nib;
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}
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void write_dev_mem( long addr, int val )
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{
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static int old_line_offset = -1;
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device_check = true;
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schedule_event = 0;
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switch ( ( int )addr ) {
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case 0x100: /* DISPIO */
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if ( val != saturn.disp_io ) {
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saturn.disp_io = val;
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display.on = ( val & 0x8 ) >> 3;
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display.offset = val & 0x7;
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if ( display.offset > 3 )
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display.nibs_per_line = ( NIBBLES_PER_ROW + saturn.line_offset + 2 ) & 0xfff;
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else
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display.nibs_per_line = ( NIBBLES_PER_ROW + saturn.line_offset ) & 0xfff;
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display.disp_end = display.disp_start + ( display.nibs_per_line * ( display.lines + 1 ) );
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device.display_touched = DISP_INSTR_OFF;
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}
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return;
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case 0x101: /* CONTRAST CONTROL */
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saturn.contrast_ctrl = val;
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display.contrast &= ~0x0f;
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display.contrast |= val;
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device.contrast_touched = true;
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return;
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case 0x102: /* DISPLAY TEST */
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display.contrast &= ~0xf0;
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display.contrast |= ( ( val & 0x1 ) << 4 );
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device.contrast_touched = true;
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/* Fall through */
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case 0x103: /* DISPLAY TEST */
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saturn.disp_test &= ~nibble_masks[ addr - 0x102 ];
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saturn.disp_test |= val << ( ( addr - 0x102 ) * 4 );
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/* device.disp_test_touched = true; */
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return;
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case 0x104:
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case 0x105:
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case 0x106:
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case 0x107: /* CRC */
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saturn.crc &= ~nibble_masks[ addr - 0x104 ];
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saturn.crc |= val << ( ( addr - 0x104 ) * 4 );
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return;
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case 0x108: /* POWER STATUS */
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saturn.power_status = val;
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/* device.power_status_touched = true; */
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return;
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case 0x109: /* POWER CONTROL */
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saturn.power_ctrl = val;
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/* device.power_ctrl_touched = true; */
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return;
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case 0x10a: /* MODE */
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saturn.mode = val;
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/* device.mode_touched = true; */
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return;
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case 0x10b:
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case 0x10c: /* ANNUNC */
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saturn.annunc &= ~nibble_masks[ addr - 0x10b ];
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saturn.annunc |= val << ( ( addr - 0x10b ) * 4 );
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device.ann_touched = true;
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return;
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case 0x10d: /* BAUD */
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saturn.baud = val;
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device.baud_touched = true;
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return;
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case 0x10e: /* CARD CONTROL */
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saturn.card_ctrl = val;
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if ( saturn.card_ctrl & 0x02 )
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saturn.MP = 1;
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if ( saturn.card_ctrl & 0x01 )
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do_interupt();
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/* device.card_ctrl_touched = true; */
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return;
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case 0x10f: /* CARD STATUS */
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return;
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case 0x110: /* IO CONTROL */
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saturn.io_ctrl = val;
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device.ioc_touched = true;
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return;
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case 0x111: /* RCS */
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saturn.rcs = val;
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return;
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case 0x112: /* TCS */
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saturn.tcs = val;
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return;
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case 0x113: /* CRER */
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saturn.rcs &= 0x0b;
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return;
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case 0x114:
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case 0x115: /* RBR */
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return;
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case 0x116:
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case 0x117: /* TBR */
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saturn.tbr &= ~nibble_masks[ addr - 0x116 ];
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saturn.tbr |= val << ( ( addr - 0x116 ) * 4 );
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saturn.tcs |= 0x01;
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device.tbr_touched = true;
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return;
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case 0x118:
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case 0x119: /* SERVICE REQ */
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saturn.sreq &= ~nibble_masks[ addr - 0x118 ];
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saturn.sreq |= val << ( ( addr - 0x118 ) * 4 );
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/* device.sreq_touched = true; */
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return;
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case 0x11a: /* IR CONTROL */
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saturn.ir_ctrl = val;
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/* device.ir_ctrl_touched = true; */
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return;
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case 0x11b: /* BASE NIB OFFSET */
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saturn.base_off = val;
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/* device.base_off_touched = true; */
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return;
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case 0x11c: /* LED CONTROL */
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saturn.lcr = val;
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/* device.lcr_touched = true; */
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return;
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case 0x11d: /* LED BUFFER */
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saturn.lbr = val;
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/* device.lbr_touched = true; */
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return;
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case 0x11e: /* SCRATCH PAD */
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saturn.scratch = val;
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/* device.scratch_touched = true; */
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return;
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case 0x11f: /* BASENIBBLE */
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saturn.base_nibble = val;
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/* device.base_nibble_touched = true; */
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return;
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case 0x120:
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case 0x121:
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case 0x122:
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case 0x123: /* DISP_ADDR */
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case 0x124:
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saturn.disp_addr &= ~nibble_masks[ addr - 0x120 ];
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saturn.disp_addr |= val << ( ( addr - 0x120 ) * 4 );
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if ( display.disp_start != ( saturn.disp_addr & 0xffffe ) ) {
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display.disp_start = saturn.disp_addr & 0xffffe;
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display.disp_end = display.disp_start + ( display.nibs_per_line * ( display.lines + 1 ) );
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device.display_touched = DISP_INSTR_OFF;
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}
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return;
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case 0x125:
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case 0x126:
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case 0x127: /* LINE_OFFSET */
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saturn.line_offset &= ~nibble_masks[ addr - 0x125 ];
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saturn.line_offset |= val << ( ( addr - 0x125 ) * 4 );
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if ( saturn.line_offset != old_line_offset ) {
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old_line_offset = saturn.line_offset;
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if ( display.offset > 3 )
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display.nibs_per_line = ( NIBBLES_PER_ROW + saturn.line_offset + 2 ) & 0xfff;
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else
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display.nibs_per_line = ( NIBBLES_PER_ROW + saturn.line_offset ) & 0xfff;
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display.disp_end = display.disp_start + ( display.nibs_per_line * ( display.lines + 1 ) );
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device.display_touched = DISP_INSTR_OFF;
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}
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return;
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case 0x128:
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case 0x129: /* LINE_COUNT */
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saturn.line_count &= ~nibble_masks[ addr - 0x128 ];
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saturn.line_count |= val << ( ( addr - 0x128 ) * 4 );
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line_counter = -1;
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if ( display.lines != ( saturn.line_count & 0x3f ) ) {
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display.lines = saturn.line_count & 0x3f;
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if ( display.lines == 0 )
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display.lines = 63;
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display.disp_end = display.disp_start + ( display.nibs_per_line * ( display.lines + 1 ) );
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device.display_touched = DISP_INSTR_OFF;
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}
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return;
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case 0x12a:
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case 0x12b:
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case 0x12c:
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case 0x12d: /* Dont know yet */
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saturn.unknown &= ~nibble_masks[ addr - 0x12a ];
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saturn.unknown |= val << ( ( addr - 0x12a ) * 4 );
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/* device.unknown_touched = true; */
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return;
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case 0x12e: /* TIMER 1 CONTROL */
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saturn.t1_ctrl = val;
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/* device.t1_ctrl_touched = true; */
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return;
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case 0x12f: /* TIMER 2 CONTROL */
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saturn.t2_ctrl = val;
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/* device.t2_ctrl_touched = true; */
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return;
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case 0x130:
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case 0x131:
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case 0x132:
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case 0x133: /* MENU_ADDR */
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case 0x134:
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saturn.menu_addr &= ~nibble_masks[ addr - 0x130 ];
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saturn.menu_addr |= val << ( ( addr - 0x130 ) * 4 );
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if ( display.menu_start != saturn.menu_addr ) {
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display.menu_start = saturn.menu_addr;
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display.menu_end = display.menu_start + 0x110;
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device.display_touched = DISP_INSTR_OFF;
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}
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return;
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case 0x135:
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case 0x136: /* Dont know yet 2 */
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saturn.unknown2 &= ~nibble_masks[ addr - 0x135 ];
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saturn.unknown2 |= val << ( ( addr - 0x135 ) * 4 );
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/* device.unknown2_touched = true; */
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return;
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case 0x137: /* TIMER1 */
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saturn.timer1 = val;
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device.t1_touched = true;
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return;
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case 0x138:
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case 0x139:
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case 0x13a:
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case 0x13b:
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case 0x13c:
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case 0x13d:
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case 0x13e:
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case 0x13f: /* TIMER2 */
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saturn.timer2 &= ~nibble_masks[ addr - 0x138 ];
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saturn.timer2 |= val << ( ( addr - 0x138 ) * 4 );
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device.t2_touched = true;
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return;
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default:
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if ( config.verbose )
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fprintf( stderr, "%.5lx: UNKNOWN DEVICE WRITE AT 0x%lx !!!\n", saturn.PC, addr );
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return;
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}
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}
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int read_dev_mem( long addr )
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{
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switch ( ( int )addr ) {
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case 0x100: /* DISPLAY IO */
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return saturn.disp_io & 0x0f;
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case 0x101: /* CONTRAST CONTROL */
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return saturn.contrast_ctrl & 0x0f;
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case 0x102:
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case 0x103: /* DISPLAY TEST */
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return ( saturn.disp_test >> ( ( addr - 0x102 ) * 4 ) ) & 0x0f;
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case 0x104:
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case 0x105:
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case 0x106:
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case 0x107: /* CRC */
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return ( saturn.crc >> ( ( addr - 0x104 ) * 4 ) ) & 0x0f;
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case 0x108: /* POWER STATUS */
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return saturn.power_status & 0x0f;
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case 0x109: /* POWER CONTROL */
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return saturn.power_ctrl & 0x0f;
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case 0x10a: /* MODE */
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return saturn.mode & 0x0f;
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case 0x10b:
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case 0x10c: /* ANNUNC */
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return ( saturn.annunc >> ( ( addr - 0x10b ) * 4 ) ) & 0x0f;
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case 0x10d: /* BAUD */
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return saturn.baud & 0x0f;
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case 0x10e: /* CARD CONTROL */
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return saturn.card_ctrl & 0x0f;
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case 0x10f: /* CARD STATUS */
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return saturn.card_status & 0x0f;
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case 0x110: /* IO CONTROL */
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return saturn.io_ctrl & 0x0f;
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case 0x111: /* RCS */
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return saturn.rcs & 0x0f;
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case 0x112: /* TCS */
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return saturn.tcs & 0x0f;
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case 0x113: /* CRER */
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return 0x00;
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case 0x114:
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case 0x115: /* RBR */
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saturn.rcs &= 0x0e;
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device.rbr_touched = true;
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device_check = true;
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schedule_event = 0;
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return ( saturn.rbr >> ( ( addr - 0x114 ) * 4 ) ) & 0x0f;
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case 0x116:
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case 0x117: /* TBR */
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return 0x00;
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case 0x118:
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case 0x119: /* SERVICE REQ */
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return ( saturn.sreq >> ( ( addr - 0x118 ) * 4 ) ) & 0x0f;
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case 0x11a: /* IR CONTROL */
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return saturn.ir_ctrl & 0x0f;
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case 0x11b: /* BASE NIB OFFSET */
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return saturn.base_off & 0x0f;
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case 0x11c: /* LED CONTROL */
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return saturn.lcr & 0x0f;
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case 0x11d: /* LED BUFFER */
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return saturn.lbr & 0x0f;
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case 0x11e: /* SCRATCH PAD */
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return saturn.scratch & 0x0f;
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case 0x11f: /* BASENIBBLE */
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return saturn.base_nibble & 0x0f;
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case 0x120:
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case 0x121:
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case 0x122:
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case 0x123: /* DISP_ADDR */
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case 0x124:
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return ( saturn.disp_addr >> ( ( addr - 0x120 ) * 4 ) ) & 0x0f;
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case 0x125:
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case 0x126:
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case 0x127: /* LINE_OFFSET */
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return ( saturn.line_offset >> ( ( addr - 0x125 ) * 4 ) ) & 0x0f;
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case 0x128:
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case 0x129: /* LINE_COUNT */
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line_counter++;
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if ( line_counter > 0x3f )
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line_counter = -1;
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return ( ( ( saturn.line_count & 0xc0 ) | ( line_counter & 0x3f ) ) >> ( ( addr - 0x128 ) * 4 ) ) & 0x0f;
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case 0x12a:
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case 0x12b:
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case 0x12c:
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case 0x12d: /* Dont know yet */
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return ( saturn.unknown >> ( ( addr - 0x12a ) * 4 ) ) & 0x0f;
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case 0x12e: /* TIMER 1 CONTROL */
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return saturn.t1_ctrl & 0x0f;
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case 0x12f: /* TIMER 2 CONTROL */
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return saturn.t2_ctrl & 0x0f;
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case 0x130:
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case 0x131:
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case 0x132:
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case 0x133: /* MENU_ADDR */
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case 0x134:
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return ( saturn.menu_addr >> ( ( addr - 0x130 ) * 4 ) ) & 0x0f;
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case 0x135:
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case 0x136: /* Dont know yet 2 */
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return ( saturn.unknown2 >> ( ( addr - 0x135 ) * 4 ) ) & 0x0f;
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case 0x137:
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return saturn.timer1 & 0xf;
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case 0x138:
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case 0x139:
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case 0x13a:
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case 0x13b:
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case 0x13c:
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case 0x13d:
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case 0x13e:
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case 0x13f:
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return ( saturn.timer2 >> ( ( addr - 0x138 ) * 4 ) ) & 0xf;
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default:
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if ( config.verbose )
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fprintf( stderr, "%.5lx: UNKNOWN DEVICE READ AT 0x%lx !!!\n", saturn.PC, addr );
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return 0x00;
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}
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}
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void write_nibble_sx( long addr, int val )
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{
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addr &= 0xfffff;
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val &= 0x0f;
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switch ( ( int )( addr >> 16 ) & 0x0f ) {
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case 0:
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if ( addr < 0x140 && addr >= 0x100 && saturn.mem_cntl[ MCTL_MMIO_SX ].config[ 0 ] == 0x100 ) {
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write_dev_mem( addr, val );
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return;
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}
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return;
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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case 6:
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return;
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case 7:
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if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 0 ] == 0x70000 ) {
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if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 1 ] == 0xfc000 && addr < 0x74000 ) {
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saturn.ram[ addr - 0x70000 ] = val;
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break;
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}
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if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 1 ] == 0xfe000 && addr < 0x72000 ) {
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saturn.ram[ addr - 0x70000 ] = val;
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break;
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}
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if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 1 ] == 0xf0000 ) {
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saturn.ram[ addr - 0x70000 ] = val;
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break;
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}
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}
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return;
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case 8:
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case 9:
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case 0xa:
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case 0xb:
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if ( saturn.mem_cntl[ MCTL_PORT1_SX ].config[ 0 ] == 0x80000 ) {
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if ( port1_is_ram )
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saturn.port1[ ( addr - 0x80000 ) & port1_mask ] = val;
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return;
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}
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if ( saturn.mem_cntl[ MCTL_PORT2_SX ].config[ 0 ] == 0x80000 ) {
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if ( port2_is_ram )
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saturn.port2[ ( addr - 0x80000 ) & port2_mask ] = val;
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return;
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}
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return;
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case 0xc:
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case 0xd:
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case 0xe:
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if ( saturn.mem_cntl[ MCTL_PORT1_SX ].config[ 0 ] == 0xc0000 ) {
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if ( port1_is_ram )
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saturn.port1[ ( addr - 0xc0000 ) & port1_mask ] = val;
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return;
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}
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if ( saturn.mem_cntl[ MCTL_PORT2_SX ].config[ 0 ] == 0xc0000 ) {
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if ( port2_is_ram )
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saturn.port2[ ( addr - 0xc0000 ) & port2_mask ] = val;
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return;
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}
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return;
|
|
case 0xf:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 0 ] == 0xf0000 ) {
|
|
saturn.ram[ addr - 0xf0000 ] = val;
|
|
break;
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_SX ].config[ 0 ] == 0xc0000 ) {
|
|
if ( port1_is_ram )
|
|
saturn.port1[ ( addr - 0xc0000 ) & port1_mask ] = val;
|
|
return;
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_SX ].config[ 0 ] == 0xc0000 ) {
|
|
if ( port2_is_ram )
|
|
saturn.port2[ ( addr - 0xc0000 ) & port2_mask ] = val;
|
|
return;
|
|
}
|
|
return;
|
|
}
|
|
|
|
if ( device.display_touched )
|
|
return;
|
|
|
|
if ( addr >= display.disp_start && addr < display.disp_end )
|
|
ui_disp_draw_nibble( addr, val );
|
|
|
|
if ( display.lines == 63 )
|
|
return;
|
|
|
|
if ( addr >= display.menu_start && addr < display.menu_end )
|
|
ui_menu_draw_nibble( addr, val );
|
|
}
|
|
|
|
void write_nibble_gx( long addr, int val )
|
|
{
|
|
addr &= 0xfffff;
|
|
val &= 0x0f;
|
|
switch ( ( int )( addr >> 16 ) & 0x0f ) {
|
|
case 0:
|
|
if ( addr < 0x140 && addr >= 0x100 && saturn.mem_cntl[ MCTL_MMIO_GX ].config[ 0 ] == 0x100 ) {
|
|
write_dev_mem( addr, val );
|
|
return;
|
|
}
|
|
return;
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
case 5:
|
|
case 6:
|
|
return;
|
|
case 4:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x40000 ) {
|
|
saturn.ram[ addr - 0x40000 ] = val;
|
|
break;
|
|
}
|
|
return;
|
|
case 7:
|
|
if ( addr >= 0x7f000 && saturn.mem_cntl[ MCTL_BANK_GX ].config[ 0 ] == 0x7f000 ) {
|
|
return;
|
|
}
|
|
if ( addr >= 0x7e000 && addr < 0x7f000 && saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 0 ] == 0x7e000 ) {
|
|
return;
|
|
}
|
|
if ( addr >= 0x7e000 && addr < 0x7f000 && saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 0 ] == 0x7e000 ) {
|
|
return;
|
|
}
|
|
return;
|
|
case 8:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x80000 ) {
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xfc000 && addr < 0x84000 ) {
|
|
saturn.ram[ addr - 0x80000 ] = val;
|
|
break;
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xfe000 && addr < 0x82000 ) {
|
|
saturn.ram[ addr - 0x80000 ] = val;
|
|
break;
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xf0000 ) {
|
|
saturn.ram[ addr - 0x80000 ] = val;
|
|
break;
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 ) {
|
|
saturn.ram[ addr - 0x80000 ] = val;
|
|
break;
|
|
}
|
|
}
|
|
return;
|
|
case 9:
|
|
if ( saturn.mem_cntl[ MCTL_BANK_GX ].config[ 0 ] == 0x90000 ) {
|
|
if ( addr < 0x91000 ) {
|
|
return;
|
|
}
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x80000 )
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 ) {
|
|
saturn.ram[ addr - 0x80000 ] = val;
|
|
break;
|
|
}
|
|
return;
|
|
case 0xa:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x80000 )
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 ) {
|
|
saturn.ram[ addr - 0x80000 ] = val;
|
|
break;
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 0 ] == 0xa0000 ) {
|
|
if ( port1_is_ram )
|
|
saturn.port1[ ( addr - 0xa0000 ) & port1_mask ] = val;
|
|
return;
|
|
}
|
|
return;
|
|
case 0xb:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x80000 )
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 ) {
|
|
saturn.ram[ addr - 0x80000 ] = val;
|
|
break;
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 0 ] == 0xb0000 ) {
|
|
if ( port2_is_ram )
|
|
saturn.port2[ ( ( saturn.bank_switch << 18 ) + ( addr - 0xb0000 ) ) & port2_mask ] = val;
|
|
return;
|
|
}
|
|
return;
|
|
case 0xc:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0xc0000 ) {
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xfc000 && addr < 0xc4000 ) {
|
|
saturn.ram[ addr - 0xc0000 ] = val;
|
|
break;
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xfe000 && addr < 0xc2000 ) {
|
|
saturn.ram[ addr - 0xc0000 ] = val;
|
|
break;
|
|
}
|
|
saturn.ram[ addr - 0xc0000 ] = val;
|
|
break;
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 0 ] == 0xc0000 ) {
|
|
if ( port1_is_ram )
|
|
saturn.port1[ ( addr - 0xc0000 ) & port1_mask ] = val;
|
|
return;
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 0 ] == 0xc0000 ) {
|
|
if ( port2_is_ram )
|
|
saturn.port2[ ( ( saturn.bank_switch << 18 ) + ( addr - 0xc0000 ) ) & port2_mask ] = val;
|
|
return;
|
|
}
|
|
return;
|
|
case 0xd:
|
|
case 0xe:
|
|
case 0xf:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0xc0000 )
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 ) {
|
|
saturn.ram[ addr - 0xc0000 ] = val;
|
|
break;
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 0 ] == 0xc0000 )
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 1 ] == 0xc0000 ) {
|
|
if ( port1_is_ram )
|
|
saturn.port1[ ( addr - 0xc0000 ) & port1_mask ] = val;
|
|
return;
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 0 ] == 0xc0000 )
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 1 ] == 0xc0000 ) {
|
|
if ( port2_is_ram )
|
|
saturn.port2[ ( ( saturn.bank_switch << 18 ) + ( addr - 0xc0000 ) ) & port2_mask ] = val;
|
|
return;
|
|
}
|
|
return;
|
|
}
|
|
|
|
if ( device.display_touched )
|
|
return;
|
|
|
|
if ( addr >= display.disp_start && addr < display.disp_end )
|
|
ui_disp_draw_nibble( addr, val );
|
|
|
|
if ( display.lines == 63 )
|
|
return;
|
|
|
|
if ( addr >= display.menu_start && addr < display.menu_end )
|
|
ui_menu_draw_nibble( addr, val );
|
|
}
|
|
|
|
int read_nibble_sx( long addr )
|
|
{
|
|
addr &= 0xfffff;
|
|
switch ( ( int )( addr >> 16 ) & 0x0f ) {
|
|
case 0:
|
|
if ( addr < 0x140 && addr >= 0x100 ) {
|
|
if ( saturn.mem_cntl[ MCTL_MMIO_SX ].config[ 0 ] == 0x100 )
|
|
return read_dev_mem( addr );
|
|
else
|
|
return 0x00;
|
|
}
|
|
return saturn.rom[ addr ];
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
case 4:
|
|
case 5:
|
|
case 6:
|
|
return saturn.rom[ addr ];
|
|
case 7:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 0 ] == 0x70000 ) {
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 1 ] == 0xfc000 && addr < 0x74000 )
|
|
return saturn.ram[ addr - 0x70000 ];
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 1 ] == 0xfe000 && addr < 0x72000 )
|
|
return saturn.ram[ addr - 0x70000 ];
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 1 ] == 0xf0000 )
|
|
return saturn.ram[ addr - 0x70000 ];
|
|
}
|
|
return saturn.rom[ addr ];
|
|
case 8:
|
|
case 9:
|
|
case 0xa:
|
|
case 0xb:
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_SX ].config[ 0 ] == 0x80000 ) {
|
|
return saturn.port1[ ( addr - 0x80000 ) & port1_mask ];
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_SX ].config[ 0 ] == 0x80000 ) {
|
|
return saturn.port2[ ( addr - 0x80000 ) & port2_mask ];
|
|
}
|
|
return 0x00;
|
|
case 0xc:
|
|
case 0xd:
|
|
case 0xe:
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_SX ].config[ 0 ] == 0xc0000 ) {
|
|
return saturn.port1[ ( addr - 0xc0000 ) & port1_mask ];
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_SX ].config[ 0 ] == 0xc0000 ) {
|
|
return saturn.port2[ ( addr - 0xc0000 ) & port2_mask ];
|
|
}
|
|
return 0x00;
|
|
case 0xf:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 0 ] == 0xf0000 )
|
|
return saturn.ram[ addr - 0xf0000 ];
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_SX ].config[ 0 ] == 0xf0000 ) {
|
|
return saturn.port1[ ( addr - 0xf0000 ) & port1_mask ];
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_SX ].config[ 0 ] == 0xf0000 ) {
|
|
return saturn.port2[ ( addr - 0xf0000 ) & port2_mask ];
|
|
}
|
|
return 0x00;
|
|
}
|
|
return 0x00;
|
|
}
|
|
|
|
int read_nibble_gx( long addr )
|
|
{
|
|
addr &= 0xfffff;
|
|
switch ( ( int )( addr >> 16 ) & 0x0f ) {
|
|
case 0:
|
|
if ( addr < 0x140 && addr >= 0x100 ) {
|
|
if ( saturn.mem_cntl[ 0 ].config[ 0 ] == 0x100 )
|
|
return read_dev_mem( addr );
|
|
else
|
|
return 0x00;
|
|
}
|
|
return saturn.rom[ addr ];
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
case 5:
|
|
case 6:
|
|
return saturn.rom[ addr ];
|
|
case 4:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x40000 )
|
|
return saturn.ram[ addr - 0x40000 ];
|
|
return saturn.rom[ addr ];
|
|
case 7:
|
|
if ( addr >= 0x7f000 && saturn.mem_cntl[ MCTL_BANK_GX ].config[ 0 ] == 0x7f000 ) {
|
|
if ( addr == 0x7f000 ) {
|
|
saturn.bank_switch = 0;
|
|
}
|
|
if ( addr >= 0x7f040 && addr < 0x7f080 ) {
|
|
saturn.bank_switch = ( addr - 0x7f040 ) / 2;
|
|
}
|
|
return 0x7;
|
|
}
|
|
if ( addr >= 0x7e000 && addr < 0x7f000 && saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 0 ] == 0x7e000 ) {
|
|
return 0x7;
|
|
}
|
|
if ( addr >= 0x7e000 && addr < 0x7f000 && saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 0 ] == 0x7e000 ) {
|
|
return 0x7;
|
|
}
|
|
return saturn.rom[ addr ];
|
|
case 8:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x80000 ) {
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xfc000 && addr < 0x84000 )
|
|
return saturn.ram[ addr - 0x80000 ];
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xfe000 && addr < 0x82000 )
|
|
return saturn.ram[ addr - 0x80000 ];
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xf0000 )
|
|
return saturn.ram[ addr - 0x80000 ];
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 )
|
|
return saturn.ram[ addr - 0x80000 ];
|
|
}
|
|
return saturn.rom[ addr ];
|
|
case 9:
|
|
if ( saturn.mem_cntl[ 0 ].config[ 0 ] == 0x90000 ) {
|
|
if ( addr < 0x91000 ) {
|
|
if ( addr == 0x90000 ) {
|
|
saturn.bank_switch = 0;
|
|
}
|
|
if ( addr >= 0x90040 && addr < 0x90080 ) {
|
|
saturn.bank_switch = ( addr - 0x90040 ) / 2;
|
|
}
|
|
return 0x7;
|
|
}
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x80000 )
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 )
|
|
return saturn.ram[ addr - 0x80000 ];
|
|
return saturn.rom[ addr ];
|
|
case 0xa:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x80000 )
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 )
|
|
return saturn.ram[ addr - 0x80000 ];
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 0 ] == 0xa0000 ) {
|
|
return saturn.port1[ ( addr - 0xa0000 ) & port1_mask ];
|
|
}
|
|
return saturn.rom[ addr ];
|
|
case 0xb:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x80000 )
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 )
|
|
return saturn.ram[ addr - 0x80000 ];
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 0 ] == 0xb0000 ) {
|
|
return saturn.port2[ ( ( saturn.bank_switch << 18 ) + ( addr - 0xb0000 ) ) & port2_mask ];
|
|
/*
|
|
if (port2_size > (saturn.bank_switch << 18))
|
|
{
|
|
return saturn.port2[(saturn.bank_switch << 18)
|
|
+ (addr - 0xb0000)];
|
|
}
|
|
return 0x00;
|
|
*/
|
|
}
|
|
return saturn.rom[ addr ];
|
|
case 0xc:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0xc0000 ) {
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xfc000 && addr < 0xc4000 )
|
|
return saturn.ram[ addr - 0xc0000 ];
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xfe000 && addr < 0xc2000 )
|
|
return saturn.ram[ addr - 0xc0000 ];
|
|
return saturn.ram[ addr - 0xc0000 ];
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 0 ] == 0xc0000 ) {
|
|
return saturn.port1[ ( addr - 0xc0000 ) & port1_mask ];
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 0 ] == 0xc0000 ) {
|
|
return saturn.port2[ ( ( saturn.bank_switch << 18 ) + ( addr - 0xc0000 ) ) & port2_mask ];
|
|
/*
|
|
if (port2_size > (saturn.bank_switch << 18))
|
|
{
|
|
return saturn.port2[(saturn.bank_switch << 18)
|
|
+ (addr - 0xc0000)];
|
|
}
|
|
return 0x00;
|
|
*/
|
|
}
|
|
return saturn.rom[ addr ];
|
|
case 0xd:
|
|
case 0xe:
|
|
case 0xf:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0xc0000 )
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 )
|
|
return saturn.ram[ addr - 0xc0000 ];
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 0 ] == 0xc0000 )
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 1 ] == 0xc0000 ) {
|
|
return saturn.port1[ ( addr - 0xc0000 ) & port1_mask ];
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 0 ] == 0xc0000 )
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 1 ] == 0xc0000 ) {
|
|
return saturn.port2[ ( ( saturn.bank_switch << 18 ) + ( addr - 0xc0000 ) ) & port2_mask ];
|
|
/*
|
|
if (port2_size > (saturn.bank_switch << 18))
|
|
{
|
|
return saturn.port2[(saturn.bank_switch <<
|
|
18)
|
|
+ (addr - 0xc0000)];
|
|
}
|
|
return 0x00;
|
|
*/
|
|
}
|
|
return saturn.rom[ addr ];
|
|
}
|
|
return 0x00;
|
|
}
|
|
|
|
int read_nibble_crc_sx( long addr )
|
|
{
|
|
addr &= 0xfffff;
|
|
switch ( ( int )( addr >> 16 ) & 0x0f ) {
|
|
case 0:
|
|
if ( addr < 0x140 && addr >= 0x100 ) {
|
|
if ( saturn.mem_cntl[ MCTL_MMIO_SX ].config[ 0 ] == 0x100 )
|
|
return read_dev_mem( addr );
|
|
else
|
|
return calc_crc( 0x00 );
|
|
}
|
|
return calc_crc( saturn.rom[ addr ] );
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
case 4:
|
|
case 5:
|
|
case 6:
|
|
return calc_crc( saturn.rom[ addr ] );
|
|
case 7:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 0 ] == 0x70000 ) {
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 1 ] == 0xfc000 && addr < 0x74000 )
|
|
return calc_crc( saturn.ram[ addr - 0x70000 ] );
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 1 ] == 0xfe000 && addr < 0x72000 )
|
|
return calc_crc( saturn.ram[ addr - 0x70000 ] );
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 1 ] == 0xf0000 )
|
|
return calc_crc( saturn.ram[ addr - 0x70000 ] );
|
|
}
|
|
return calc_crc( saturn.rom[ addr ] );
|
|
case 8:
|
|
case 9:
|
|
case 0xa:
|
|
case 0xb:
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_SX ].config[ 0 ] == 0x80000 ) {
|
|
return calc_crc( saturn.port1[ ( addr - 0x80000 ) & port1_mask ] );
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_SX ].config[ 0 ] == 0x80000 ) {
|
|
return calc_crc( saturn.port2[ ( addr - 0x80000 ) & port2_mask ] );
|
|
}
|
|
return 0x00;
|
|
case 0xc:
|
|
case 0xd:
|
|
case 0xe:
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_SX ].config[ 0 ] == 0xc0000 ) {
|
|
return calc_crc( saturn.port1[ ( addr - 0xc0000 ) & port1_mask ] );
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_SX ].config[ 0 ] == 0xc0000 ) {
|
|
return calc_crc( saturn.port2[ ( addr - 0xc0000 ) & port2_mask ] );
|
|
}
|
|
return 0x00;
|
|
case 0xf:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_SX ].config[ 0 ] == 0xf0000 )
|
|
return calc_crc( saturn.ram[ addr - 0xf0000 ] );
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_SX ].config[ 0 ] == 0xc0000 ) {
|
|
return calc_crc( saturn.port1[ ( addr - 0xc0000 ) & port1_mask ] );
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_SX ].config[ 0 ] == 0xc0000 ) {
|
|
return calc_crc( saturn.port2[ ( addr - 0xc0000 ) & port2_mask ] );
|
|
}
|
|
return 0x00;
|
|
}
|
|
return 0x00;
|
|
}
|
|
|
|
int read_nibble_crc_gx( long addr )
|
|
{
|
|
addr &= 0xfffff;
|
|
switch ( ( int )( addr >> 16 ) & 0x0f ) {
|
|
case 0:
|
|
if ( addr < 0x140 && addr >= 0x100 ) {
|
|
if ( saturn.mem_cntl[ MCTL_MMIO_GX ].config[ 0 ] == 0x100 )
|
|
return read_dev_mem( addr );
|
|
else
|
|
return calc_crc( 0x00 );
|
|
}
|
|
return calc_crc( saturn.rom[ addr ] );
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
case 5:
|
|
case 6:
|
|
return calc_crc( saturn.rom[ addr ] );
|
|
case 4:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x40000 )
|
|
return calc_crc( saturn.ram[ addr - 0x40000 ] );
|
|
return calc_crc( saturn.rom[ addr ] );
|
|
case 7:
|
|
if ( addr >= 0x7f000 && saturn.mem_cntl[ MCTL_BANK_GX ].config[ 0 ] == 0x7f000 ) {
|
|
if ( addr == 0x7f000 ) {
|
|
saturn.bank_switch = 0;
|
|
}
|
|
if ( addr >= 0x7f040 && addr < 0x7f080 ) {
|
|
saturn.bank_switch = ( addr - 0x7f040 ) / 2;
|
|
}
|
|
return 0x7;
|
|
}
|
|
if ( addr >= 0x7e000 && addr < 0x7f000 && saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 0 ] == 0x7e000 ) {
|
|
return 0x7;
|
|
}
|
|
if ( addr >= 0x7e000 && addr < 0x7f000 && saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 0 ] == 0x7e000 ) {
|
|
return 0x7;
|
|
}
|
|
return calc_crc( saturn.rom[ addr ] );
|
|
case 8:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x80000 ) {
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xfc000 && addr < 0x84000 )
|
|
return calc_crc( saturn.ram[ addr - 0x80000 ] );
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xfe000 && addr < 0x82000 )
|
|
return calc_crc( saturn.ram[ addr - 0x80000 ] );
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xf0000 )
|
|
return calc_crc( saturn.ram[ addr - 0x80000 ] );
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 )
|
|
return calc_crc( saturn.ram[ addr - 0x80000 ] );
|
|
}
|
|
return calc_crc( saturn.rom[ addr ] );
|
|
case 9:
|
|
if ( saturn.mem_cntl[ 0 ].config[ 0 ] == 0x90000 ) {
|
|
if ( addr < 0x91000 ) {
|
|
if ( addr == 0x90000 ) {
|
|
saturn.bank_switch = 0;
|
|
}
|
|
if ( addr >= 0x90040 && addr < 0x90080 ) {
|
|
saturn.bank_switch = ( addr - 0x90040 ) / 2;
|
|
}
|
|
return 0x7;
|
|
}
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x80000 )
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 )
|
|
return calc_crc( saturn.ram[ addr - 0x80000 ] );
|
|
return calc_crc( saturn.rom[ addr ] );
|
|
case 0xa:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x80000 )
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 )
|
|
return calc_crc( saturn.ram[ addr - 0x80000 ] );
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 0 ] == 0xa0000 ) {
|
|
return calc_crc( saturn.port1[ ( addr - 0xa0000 ) & port1_mask ] );
|
|
}
|
|
return calc_crc( saturn.rom[ addr ] );
|
|
case 0xb:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0x80000 )
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 )
|
|
return calc_crc( saturn.ram[ addr - 0x80000 ] );
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 0 ] == 0xb0000 ) {
|
|
return calc_crc( saturn.port2[ ( ( saturn.bank_switch << 18 ) + ( addr - 0xb0000 ) ) & port2_mask ] );
|
|
/*
|
|
if (port2_size > (saturn.bank_switch << 18))
|
|
{
|
|
return calc_crc(saturn.port2[(saturn.bank_switch
|
|
<< 18)
|
|
+ (addr -
|
|
0xb0000)]);
|
|
}
|
|
return 0x00;
|
|
*/
|
|
}
|
|
return calc_crc( saturn.rom[ addr ] );
|
|
case 0xc:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0xc0000 ) {
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xfc000 && addr < 0xc4000 )
|
|
return calc_crc( saturn.ram[ addr - 0xc0000 ] );
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xfe000 && addr < 0xc2000 )
|
|
return calc_crc( saturn.ram[ addr - 0xc0000 ] );
|
|
return calc_crc( saturn.ram[ addr - 0xc0000 ] );
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 0 ] == 0xc0000 ) {
|
|
return calc_crc( saturn.port1[ ( addr - 0xc0000 ) & port1_mask ] );
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 0 ] == 0xc0000 ) {
|
|
return calc_crc( saturn.port2[ ( ( saturn.bank_switch << 18 ) + ( addr - 0xc0000 ) ) & port2_mask ] );
|
|
/*
|
|
if (port2_size > (saturn.bank_switch << 18))
|
|
{
|
|
return calc_crc(saturn.port2[(saturn.bank_switch
|
|
<< 18)
|
|
+ (addr -
|
|
0xc0000)]);
|
|
}
|
|
return 0x00;
|
|
*/
|
|
}
|
|
return calc_crc( saturn.rom[ addr ] );
|
|
case 0xd:
|
|
case 0xe:
|
|
case 0xf:
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 0 ] == 0xc0000 )
|
|
if ( saturn.mem_cntl[ MCTL_SysRAM_GX ].config[ 1 ] == 0xc0000 )
|
|
return calc_crc( saturn.ram[ addr - 0xc0000 ] );
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 0 ] == 0xc0000 )
|
|
if ( saturn.mem_cntl[ MCTL_PORT1_GX ].config[ 1 ] == 0xc0000 ) {
|
|
return calc_crc( saturn.port1[ ( addr - 0xc0000 ) & port1_mask ] );
|
|
}
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 0 ] == 0xc0000 )
|
|
if ( saturn.mem_cntl[ MCTL_PORT2_GX ].config[ 1 ] == 0xc0000 ) {
|
|
return calc_crc( saturn.port2[ ( ( saturn.bank_switch << 18 ) + ( addr - 0xc0000 ) ) & port2_mask ] );
|
|
/*
|
|
if (port2_size > (saturn.bank_switch << 18))
|
|
{
|
|
return
|
|
calc_crc(saturn.port2[(saturn.bank_switch << 18)
|
|
+ (addr -
|
|
0xc0000)]);
|
|
}
|
|
return 0x00;
|
|
*/
|
|
}
|
|
return calc_crc( saturn.rom[ addr ] );
|
|
}
|
|
return 0x00;
|
|
}
|
|
|
|
long read_nibbles( long addr, int len )
|
|
{
|
|
long val = 0;
|
|
|
|
addr += len;
|
|
while ( len-- > 0 )
|
|
val = ( val << 4 ) | read_nibble( --addr );
|
|
|
|
return val;
|
|
}
|
|
|
|
void dev_memory_init( void )
|
|
{
|
|
if ( opt_gx ) {
|
|
read_nibble = read_nibble_gx;
|
|
read_nibble_crc = read_nibble_crc_gx;
|
|
write_nibble = write_nibble_gx;
|
|
} else {
|
|
read_nibble = read_nibble_sx;
|
|
read_nibble_crc = read_nibble_crc_sx;
|
|
write_nibble = write_nibble_sx;
|
|
}
|
|
|
|
memset( &device, 0, sizeof( device ) );
|
|
}
|