af664bab5f
Signed-off-by: Gwenhael Le Moine <gwenhael.le.moine@gmail.com>
56 lines
2.7 KiB
Text
56 lines
2.7 KiB
Text
Known bugs and restrictions of Emu48 V1.49
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- the following I/O bits aren't emulated (incomplete)
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DTEST (0x102) [VDIG LID TRIM]
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DSPCTL (0x103) [LRT LRTD LRTC BIN]
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LPD (0x108) [LB2 LB1]
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LPE (0x109) [GRST RST]
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CMODE (0x10A) Mode register
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IOC (0x110) [ERBZ]
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RCS (0x111) [RX RER RBZ]
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SRQ1 (0x118) [ISQR]
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SRQ2 (0x119) [LSRQ]
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IRC (0x11A) [IRI EIRU EIRI IRE]
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LCR (0x11C) [LED ELBE LBZ LBF]
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LBR (0x11D) [LBO]
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- the baudrates 1920, 3840, 7680 and 15360 aren't emulated on most
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operating systems
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Windows 95a 1920, 3840, 7680 work, 15360 fail
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Windows 98, NT4.0, 2000, XP all baudrates fail
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- problems when receiving a break signal on the serial port
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Windows 98, NT4.0 SP4 no retrigger on port open
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Windows 98 timing problems setting the RER bit
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Windows 2000 SP2 no known problems
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- System-RPL commands VERYVERYSLOW, VERYSLOW and SLOW depends on PC
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speed (are realized as simple down counter in ROM)
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- display updating differs from the real machine
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- screen VBL counter values may skip after large display operations
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like turning on or updating the whole display
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- executing an opcode over a MMU boundary will fail
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- read on an unconfigured address (open data bus) will not show the
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same value like a real calculator
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- the Yorke hardware signals BEN and DA19 aren't fully supported,
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because the emulator don't use a multiplexed AR18 / NCE3 data line
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-> all programs that run on a real calculator will run as well,
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programs with incorrect DA19 / BEN handling may run on the
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emulator but will crash on a real calculator
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- incomplete reset logic of the bank switcher FF, on real
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calculators a reset happen after about 4s in deep sleep, in the
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emulator this happens immediately
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- no MP interrupt on card control circuit or timer restart
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- no beeper support with OUT command -> all programs that aren't
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use the "=makebeep" subroutine, like alarm wake up, have no sound
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- beeper emulation, ATTN key doesn't work
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- no infrared printer support
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- Shell OS: clock isn't synchronized with real time
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- HP49G: the flash memory is emulated now with some restrictions
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- no flash programming times, the flash state machine returns
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immediately the ready signal
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- only one write buffer, second not needed because of prior reason
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- not fully tested, especially the status byte may return
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incorrect values (error bits)
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- quitting the emulator while programming the flash isn't allowed,
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because the content of flash state machine isn't saved so far
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08/18/09 (c) by Christoph Gie<69>elink, c dot giesselink at gmx dot de
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