474 lines
14 KiB
C
474 lines
14 KiB
C
/*
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* apple.c
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*
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* This file is part of Emu48
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*
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* Copyright (C) 2005 CdB for HP
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* Copyright (C) 2006 Christoph Gießelink
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*
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*/
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#include "pch.h"
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#include "Emu48.h"
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#include "Opcodes.h"
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#include "apple.h"
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#include "io.h" // I/O register definitions
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#include "i28f160.h"
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#define w Chipset
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#pragma intrinsic(memset,memcpy)
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#include "Ops.h"
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//
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// ROM buffer access functions
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//
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static __inline void WrDirtyPage(DWORD d)
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{
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if (pbyRomDirtyPage) // using dirty ROM page table
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{
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DWORD dwPage = d / ROMPAGESIZE; // this is the page
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_ASSERT(dwPage < dwRomDirtyPageSize);
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pbyRomDirtyPage[dwPage] = TRUE; // page is dirty
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}
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return;
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}
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static __inline void EraseBlock(DWORD d,DWORD dwNibSize)
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{
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LPBYTE pbyAddr = pbyRom + d;
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while (dwNibSize--)
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{
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WrDirtyPage(d++); // make page dirty
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*pbyAddr++ = 0x0F; // clear address
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}
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return;
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}
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static CONST LPBYTE ppReg[] = { w.A, w.B, w.C, w.D };
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static QWORD DecodeReg64(LPBYTE R, BYTE byNF)
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{
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QWORD qwVal = Npack64(R,16); // generate 64bit number from register
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switch (byNF) // field selector
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{
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case 0: return (qwVal >> (w.P*4)) & 0xf; // P
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case 1: return qwVal & ~((QWORD)~0 << ((w.P+1)*4));// WP
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case 2: return (qwVal >> 8) & 0xf; // XS
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case 3: return qwVal & 0xfff; // X
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case 4: return (qwVal >> 60) & 0xf; // S
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case 5: return (qwVal >> 12) & 0x0000ffffffffffff; // M
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case 6: return qwVal & 0xff; // B
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case 7: return qwVal; // W
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case 15: return qwVal & 0xfffff; // A
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// default: return qwVal & w.fld[byNF-8]; // F1-F7
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default: return qwVal;
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}
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}
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static void EncodeReg64(QWORD v, LPBYTE R, BYTE byNF)
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{
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if (byNF > 7 && byNF < 15) // user mask area F1-F7
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{
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// QWORD qwMask = w.fld[byNF-8]; // F1-F7
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// QWORD qwVal = Npack64(R,16); // original content of register
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// v = (v & qwMask) | (qwVal & ~qwMask); // mask operation
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byNF = 7; // write W area
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}
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Nunpack64(R+F_s[byNF], v, F_l[byNF]);
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return;
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}
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static QWORD o80BReg164(LPBYTE I)
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{
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_ASSERT((I[5] & 3) < ARRAYSIZEOF(ppReg));
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return DecodeReg64(ppReg[I[5] & 3], I[6]);
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}
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static QWORD o80BReg264(LPBYTE I)
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{
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_ASSERT((I[5] >> 2) < ARRAYSIZEOF(ppReg));
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return DecodeReg64(ppReg[I[5] >> 2], I[6]);
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}
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static void o80BRegWrite(QWORD v, LPBYTE I)
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{
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_ASSERT((I[5] & 3) < ARRAYSIZEOF(ppReg));
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EncodeReg64(v, ppReg[I[5] & 3], I[6]);
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return;
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}
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// SETFLDx
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VOID o80BF7x(LPBYTE I)
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{
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QWORD qwVal;
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_ASSERT(FALSE); // not tested so far
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w.pc+=1; // skip x nibble
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qwVal = Npack64(w.C,16); // generate 64bit number from C register
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w.carry = (qwVal == 0) // set carry if field mask = 0
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|| (I[5] < 8) || (I[5] > 14); // or x argument not in range 8..15
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if (!w.carry) // field mask and argument are valid
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{
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_ASSERT(I[5] >= 8 && I[5] <= 14);
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// w.fld[I[5]-8] = qwVal;
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}
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return;
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}
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// RPL2 (normal LOOP with preserving Carry)
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VOID o80B00(VOID)
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{
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BYTE p[5];
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Nread(w.A, w.d0, 5); // A=DAT0 A
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w.d0 = (w.d0 + 5) & 0xFFFFF; // D0=D0+ 5
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Nread(p, Npack(w.A,5), 5); // PC=(A)
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w.pc = Npack(p,5);
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return;
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}
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// FALSE +5
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VOID o80B30(VOID)
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{
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Ndec(w.D, 5, 0); // D=D-1 A
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if (w.carry) w.pc = 0x03A9B; // memerr?
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w.d1 -= 5; // D1=D1- 5 (don't care about carry here)
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Nwrite(w.A, w.d1, 5); // DAT1=A A
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o80B00(); // LOOP
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return;
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}
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// DOFALSE
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VOID o80B40(VOID)
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{
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w.P = 0; // P= 0
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PCHANGED;
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Nunpack(w.C,0x03AC0,5); // LC(5) =FALSE
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memcpy(w.A, w.C, 5); // A=C A
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o80B30(); // PC=(A) (call FALSE)
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return;
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}
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// BEEP2
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VOID o80B50(CHIPSET* w)
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{
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BYTE fbeep;
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DWORD freq,dur;
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freq = Npack(w->D,5); // frequency in Hz
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dur = Npack(w->C,5); // duration in ms
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Nread(&fbeep,0x80F0F,1); // fetch system flags -53 to -56
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w->carry = TRUE; // setting of no beep
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if (!(fbeep & 0x8) && freq) // bit -56 clear and frequency > 0 Hz
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{
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if (freq > 4400) freq = 4400; // high limit of HP (SX)
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SoundBeep(freq,dur); // beeping
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// estimate cpu cycles for beeping time (4MHz)
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w->cycles += dur * 4000;
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// original routine return with...
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w->P = 0; // P=0
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w->intk = TRUE; // INTON
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w->carry = FALSE; // RTNCC
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}
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w->pc = rstkpop();
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return;
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}
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// MOVEDOWN
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VOID o80B60(VOID)
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{
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BYTE byData[16];
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DWORD dwC,s;
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for (dwC = Npack(w.C,5); dwC > 0; dwC -= s)
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{
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s = ARRAYSIZEOF(byData); // max size for data
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if (dwC < s) s = dwC;
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Npeek(byData,w.d0,s); // read source without CRC update
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Nwrite(byData,w.d1,s); // write destination
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w.d0 = (w.d0 + s) & 0xFFFFF;
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w.d1 = (w.d1 + s) & 0xFFFFF;
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}
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w.P = 0;
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PCHANGED;
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w.carry = FALSE;
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return;
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}
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// MOVEUP
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VOID o80B70(VOID)
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{
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BYTE byData[16];
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DWORD dwC,s;
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for (dwC = Npack(w.C,5); dwC > 0; dwC -= s)
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{
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s = ARRAYSIZEOF(byData); // max size for data
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if (dwC < s) s = dwC;
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w.d0 = (w.d0 - s) & 0xFFFFF;
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w.d1 = (w.d1 - s) & 0xFFFFF;
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Npeek(byData,w.d0,s); // read source without CRC update
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Nwrite(byData,w.d1,s); // write destination
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}
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w.P = 0;
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PCHANGED;
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w.carry = FALSE;
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return;
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}
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// CREATETEMP
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VOID o80B80(VOID)
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{
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DWORD dwC,dwAddress;
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dwC = Npack(w.C,5); // desired size of hole
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dwAddress = RPL_CreateTemp(dwC,FALSE); // allocate memory
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if (dwAddress)
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{
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w.d0 = dwAddress; // object position
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w.d1 = (w.d0 + dwC) & 0xFFFFF; // link field of hole
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w.carry = FALSE; // no error
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}
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else
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{
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w.carry = TRUE; // error
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}
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dwC += 6; // desired size + link field
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Nunpack(w.B,dwC,5); // B[A] = size + 6
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Nunpack(w.C,dwC,5); // C[A] = size + 6
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return;
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}
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// RCKBp
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VOID o80B90(CHIPSET* w) // ROM Check Beep patch
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{
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DWORD dw2F,dwCpuFreq;
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DWORD freq,dur;
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BYTE f,d;
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f = w->C[1]; // f = freq ctl
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d = w->C[0]; // d = duration ctl
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// CPU strobe frequency @ RATE 27 = 3.67MHz
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// CPU strobe frequency @ RATE 29 = 3.93MHz
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dwCpuFreq = ((27 + 1) * 524288) >> 2;
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dw2F = f * 180 + 367; // F=f*90+183.5
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freq = dwCpuFreq / dw2F;
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dur = (dw2F * (256 - 16 * d)) * 1000 / 2 / dwCpuFreq;
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if (freq > 4400) freq = 4400; // high limit of HP
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SoundBeep(freq,dur); // beeping
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// estimate cpu cycles for beeping time (4MHz)
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w->cycles += dur * 4000;
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w->P = 0; // P=0
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w->carry = FALSE; // RTNCC
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w->pc = rstkpop();
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return;
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}
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// setup basic memory configuration
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VOID o80B04(VOID)
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{
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DWORD a;
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a = Npack(w.C,5); // save C[A]
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Reset(); // unconfig all devices
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Nunpack(w.C,0x100,5); // IO: 0x00100
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Config(); // addr
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Nunpack(w.C,0x80000,5); // RAM: 0x80000 size 256KB
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Config(); // size
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Config(); // addr
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Nunpack(w.C,a,5); // restore C[A]
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w.P = 0;
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PCHANGED;
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return;
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}
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// erase flash bank
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VOID o80B14(VOID)
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{
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DWORD dwStart,dwStop;
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BYTE byBank = w.C[15]; // C[S] = bank to erase
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_ASSERT(FALSE); // not tested so far
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// ROM is logically organized in 16 banks with 128KB
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dwStart = byBank * _KB(128); // start address
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dwStop = dwStart + _KB(128); // last address
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if (byBank == 0) dwStart += _KB(64); // skip boot loader
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// clear bank
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EraseBlock(dwStart,dwStop-dwStart);
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w.carry = FALSE; // no error
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return;
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}
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// write bytes to flash
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VOID o80B24(VOID)
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{
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LPBYTE pbyBuffer;
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DWORD dwNib,dwAddr,dwSize;
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dwNib = Npack(w.C,5) * 2; // no. of nibbles to copy
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dwAddr = FlashROMAddr(w.d1); // linear addr in flash chip
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dwSize = dwRomSize - dwAddr; // remaining memory size in flash
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if (dwNib > dwSize) dwNib = dwSize; // prevent buffer overflow
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pbyBuffer = (LPBYTE) malloc(dwNib); // allocate data buffer
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if (pbyBuffer != NULL)
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{
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DWORD i;
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Npeek(pbyBuffer,w.d0,dwNib); // get data
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for (i = 0; i < dwNib; ++i)
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{
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WrDirtyPage(dwAddr); // make page dirty
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pbyRom[dwAddr++] = pbyBuffer[i]; // write data
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}
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free(pbyBuffer);
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}
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w.d0 += dwNib; // update source register
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w.d1 += dwNib; // update destination register
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w.carry = FALSE; // no error
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return;
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}
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// OUTBYT
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VOID o80B65(VOID)
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{
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// set Transmitting annunciator
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BYTE byAnn = w.IORam[ANNCTRL+1] | 0x2;
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WriteIO(&byAnn,ANNCTRL+1,1);
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SendByteUdp((BYTE) Npack(w.A,2)); // send data byte
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w.P = 0;
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PCHANGED;
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w.carry = FALSE; // no error
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return;
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}
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// CdB for HP: add apples BUSCC commands
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VOID o80BExt(LPBYTE I) // Saturnator extentions
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{
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DWORD a;
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w.pc+=2;
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switch (I[3]+(I[4]<<4))
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{
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case 0x00: o80B00(); break; // RPL2 (preserve Carry)
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case 0x03: o80B30(); break; // FALSE
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case 0x04: o80B40(); break; // DOFALSE
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case 0x05: o80B50(&w); PCHANGED; break; // BEEP2 implemented using Emu48's beep
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case 0x06: o80B60(); break; // MOVEDOWN
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case 0x07: o80B70(); break; // MOVEUP
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case 0x08: o80B80(); break; // CREATETEMP
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case 0x09: o80B90(&w); PCHANGED; break; // RCKBp (ROM Check Beep patch)
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case 0x0A: break; // KEYDN not implemented
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case 0x0B: break; // no doslow implemented
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case 0x10: // simulate off function
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{
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BOOL bShutdn = TRUE; // shut down
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// only shut down when no timer wake up
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if (w.IORam[TIMER1_CTRL]&WKE) // WKE bit of timer1 is set
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{
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if (ReadT1()&0x08) // and MSB of timer1 is set
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{
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w.IORam[TIMER1_CTRL] &= ~WKE; // clear WKE
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bShutdn = FALSE; // don't shut down
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}
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}
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if (w.IORam[TIMER2_CTRL]&WKE) // WKE bit of timer2 is set
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{
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if (ReadT2()&0x80000000) // and MSB of timer2 is set
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{
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w.IORam[TIMER2_CTRL] &= ~WKE; // clear WKE
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bShutdn = FALSE; // don't shut down
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}
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}
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if (w.in==0 && bShutdn) // shut down only when enabled
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{
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w.Shutdn = TRUE; // set mode before exit emulation loop
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bInterrupt = TRUE;
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}
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}
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break;
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case 0x11: w.pc+=2; break; // do not do gettime, just skip the RTN after it to fall in the normal gettime function (only valid in untouched ROM)
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case 0x12: break; // do not do settime, fall in the normal settime function (only valid in untouched ROM)
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case 0x13: break; // RESETOS not implemented
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case 0x14: break; // AUTOTEST not implemented
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case 0x15: break; // NATIVE? not implemented
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case 0x17: break; // SERIAL not implemented
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case 0x28: w.HST |= I[5]; w.pc+=1; break; // HST=1.x
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case 0x29: w.A[4]= w.A[3]= w.A[2]= w.A[0]= 0; if (cCurrentRomType=='Q') w.A[1]=5; else w.A[1]=4; break; // screen height = 0x50 = 80
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case 0x2A: w.A[4]= w.A[3]= w.A[2]= 0; w.A[1]=8; w.A[0]=3; break; // screen width = 0x83 = 131
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case 0x2B: w.carry = (cCurrentRomType == '2'); break; // it is medium apple
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case 0x2C: w.carry = (cCurrentRomType == 'Q'); break; // it is big apple
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case 0x2E: w.carry = (nCurrentClass == 50); break; // it is big apple V2
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case 0x30: w.d0address= Npack(w.C,5)>>12; Map(0,0xff); break; //config_disp0 Ca:address 4K data
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case 0x31: w.d0address=0; Map(0,0xff); RefreshDisp0(); break; //unconfig_disp0 does the refresh
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case 0x32: RefreshDisp0(); break; //refresh_disp0 force refresh
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case 0x33: a= Npack(w.C,2); if (a>(DWORD)SCREENHEIGHT) a= SCREENHEIGHT; /* w.lcounter = (SCREENHEIGHT-a) */; w.d0size= a; RefreshDisp0(); break; //set_lines_disp0 nb in Cb
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case 0x34: w.d0offset= Npack(w.C,5); w.d0offset &= 0x7FF; break; //set_offset_disp0 offset to disp in disp0
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case 0x35: Nunpack(w.C,w.d0offset,5); break; // native_get_line_disp0
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case 0x38: w.HST |= I[5]; w.pc+=3; break; // ?HST=1.x not implemented
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case 0x40: o80B04(); break; // setup basic memory configuration
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// case 0x41: o80B14(); break; // erase flash bank
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case 0x42: o80B24(); break; // write bytes into flash
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// case 0x43: ??? // format flash bank
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case 0x50: break; // REMON not implemented
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case 0x51: break; // REMOFF not implemented
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case 0x56: o80B65(); break; // OUTBYT
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case 0x57: w.D[0]= w.D[1]= 0; break;
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case 0x60: break; // ACCESSSD not implemented
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case 0x61: break; // PORTTAG? not implemented
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case 0x64: w.carry = FALSE; break; // no SD card inserted
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case 0x66: w.carry = FALSE; break; // simulate format fail card inserted
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case 0x7F: w.carry = TRUE; w.pc+=1; break; // SETFLDn not implemented, set carry for failed
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case 0x80: { QWORD b = o80BReg264(I); o80BRegWrite(b, I); w.pc+=2; break; } // r=s
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case 0x81: { QWORD a = o80BReg164(I); QWORD b = o80BReg264(I); o80BRegWrite(a+b, I); w.pc+=2; break; } // r=r+s
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case 0x82: { QWORD a = o80BReg164(I); QWORD b = o80BReg264(I); o80BRegWrite(a-b, I); w.pc+=2; break; } // r=r-s
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case 0x83: { QWORD a = o80BReg164(I); QWORD b = o80BReg264(I); o80BRegWrite(a*b, I); w.pc+=2; break; } // r=r*s
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case 0x84: { QWORD a = o80BReg164(I); QWORD b = o80BReg264(I); o80BRegWrite(a/b, I); w.pc+=2; break; } // r=r/s
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case 0x85: { QWORD a = o80BReg164(I); QWORD b = o80BReg264(I); o80BRegWrite(a%b, I); w.pc+=2; break; } // r=r%s
|
|
case 0x86: { QWORD b = o80BReg264(I); o80BRegWrite(~b, I); w.pc+=2; break; } // r=-r-1
|
|
case 0x87: { QWORD b = o80BReg264(I); o80BRegWrite((QWORD)(-(__int64)b), I); w.pc+=2; break; } // r=-r
|
|
case 0x88: { QWORD a = o80BReg164(I); QWORD b = o80BReg264(I); o80BRegWrite(a<<b, I); w.pc+=2; break; } // r=r<s
|
|
case 0x89: { QWORD a = o80BReg164(I); QWORD b = o80BReg264(I); o80BRegWrite(a>>b, I); w.pc+=2; break; } // r=r>s
|
|
case 0x8A: { QWORD a = o80BReg164(I); QWORD b = o80BReg264(I); o80BRegWrite(a^b, I); w.pc+=2; break; } // r=r^s
|
|
case 0x90: break; // data streamer not implemented
|
|
case 0xEE: break; // ARMFLUSH not implemented
|
|
case 0xEF: break; // ARMSYS not implemented
|
|
case 0xFF: break; // ARMSAT not implemented
|
|
default: w.pc-= 2;
|
|
}
|
|
return;
|
|
}
|