2024-03-19 22:24:30 +01:00
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/*
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* timer.c
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*
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* This file is part of Emu48
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*
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* Copyright (C) 1995 Sebastien Carlier
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*
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*/
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#include "pch.h"
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#include "Emu48.h"
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2024-03-19 22:37:03 +01:00
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#include "ops.h"
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2024-03-19 22:36:03 +01:00
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#include "io.h" // I/O definitions
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2024-03-19 22:24:30 +01:00
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2024-03-19 22:25:45 +01:00
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#define AUTO_OFF 10 // Time in minutes for 'auto off'
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2024-03-19 22:24:30 +01:00
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2024-03-19 22:25:45 +01:00
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// Ticks for 01.01.1970 00:00:00
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2024-03-19 22:38:33 +01:00
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#define UNIX_0_TIME ((ULONGLONG) 0x0001cf2e8f800000)
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2024-03-19 22:24:30 +01:00
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2024-03-19 22:25:45 +01:00
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// Ticks for 'auto off'
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2024-03-19 22:38:33 +01:00
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#define OFF_TIME ((ULONGLONG) (AUTO_OFF * 60) << 13)
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2024-03-19 22:24:30 +01:00
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2024-03-19 22:25:45 +01:00
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// memory address for clock and auto off
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// S(X) = 0x70052-0x70070, G(X) = 0x80058-0x80076, 49G = 0x80058-0x80076
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2024-03-19 22:24:30 +01:00
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#define RPLTIME ((cCurrentRomType=='S')?0x52:0x58)
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2024-03-19 22:25:45 +01:00
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#define T1_FREQ 62 // Timer1 1/frequency in ms
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#define T2_FREQ 8192 // Timer2 frequency
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2024-03-19 22:24:30 +01:00
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static BOOL bStarted = FALSE;
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2024-03-19 22:25:45 +01:00
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static BOOL bOutRange = FALSE; // flag if timer value out of range
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2024-03-19 22:24:30 +01:00
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static UINT uT1TimerId = 0;
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static UINT uT2TimerId = 0;
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2024-03-19 22:36:03 +01:00
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static BOOL bNINT2T1 = FALSE; // state of NINT2 affected from timer1
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static BOOL bNINT2T2 = FALSE; // state of NINT2 affected from timer2
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2024-03-19 22:25:45 +01:00
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static BOOL bAccurateTimer; // flag if accurate timer is used
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static LARGE_INTEGER lT2Ref; // counter value at timer2 start
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static TIMECAPS tc; // timer information
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2024-03-19 23:33:35 +01:00
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static UINT uT2MaxTicks; // max. timer2 ticks handled by one timer event
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2024-03-19 22:24:30 +01:00
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2024-03-19 22:38:33 +01:00
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static DWORD dwT2Ref; // timer2 value at last timer2 access
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static DWORD dwT2Cyc; // cpu cycle counter at last timer2 access
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2024-03-19 22:24:30 +01:00
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static void CALLBACK TimeProc(UINT uEventId, UINT uMsg, DWORD dwUser, DWORD dw1, DWORD dw2);
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2024-03-19 22:25:45 +01:00
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static DWORD CalcT2(VOID) // calculate timer2 value
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2024-03-19 22:24:30 +01:00
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{
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DWORD dwT2 = Chipset.t2; // get value from chipset
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if (bStarted) // timer2 running
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{
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LARGE_INTEGER lT2Act;
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DWORD dwT2Dif;
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2024-03-19 22:38:33 +01:00
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// timer should run a little bit faster (10%) than maschine in authentic speed mode
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DWORD dwCycPerTick = (9 * T2CYCLES) / 5;
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2024-03-19 22:24:30 +01:00
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QueryPerformanceCounter(&lT2Act); // actual time
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2024-03-19 22:37:54 +01:00
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// calculate realtime timer2 ticks since reference point
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dwT2 -= (DWORD)
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(((lT2Act.QuadPart - lT2Ref.QuadPart) * T2_FREQ)
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/ lFreq.QuadPart);
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dwT2Dif = dwT2Ref - dwT2; // timer2 ticks since last request
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// checking if the MSB of dwT2Dif can be used as sign flag
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_ASSERT((DWORD) tc.wPeriodMax < ((1<<(sizeof(dwT2Dif)*8-1))/8192)*1000);
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// 2nd timer call in a 32ms time frame or elapsed time is negative (Win2k bug)
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2024-03-19 22:38:33 +01:00
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if (!Chipset.Shutdn && ((dwT2Dif > 0x01 && dwT2Dif <= 0x100) || (dwT2Dif & 0x80000000) != 0))
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{
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DWORD dwT2Ticks = ((DWORD) (Chipset.cycles & 0xFFFFFFFF) - dwT2Cyc) / dwCycPerTick;
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// estimated < real elapsed timer2 ticks or negative time
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if (dwT2Ticks < dwT2Dif || (dwT2Dif & 0x80000000) != 0)
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{
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// real time too long or got negative time elapsed
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dwT2 = dwT2Ref - dwT2Ticks; // estimated timer2 value from CPU cycles
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dwT2Cyc += dwT2Ticks * dwCycPerTick; // estimated CPU cycles for the timer2 ticks
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}
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else
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{
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// reached actual time -> new synchronizing
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dwT2Cyc = (DWORD) (Chipset.cycles & 0xFFFFFFFF) - dwCycPerTick;
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}
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}
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else
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{
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// valid actual time -> new synchronizing
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dwT2Cyc = (DWORD) (Chipset.cycles & 0xFFFFFFFF) - dwCycPerTick;
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}
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dwT2Ref = dwT2; // new reference time
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}
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return dwT2;
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}
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2024-03-19 22:25:45 +01:00
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static VOID CheckT1(BYTE nT1)
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{
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// implementation of TSRQ
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bNINT2T1 = (Chipset.IORam[TIMER1_CTRL]&INTR) != 0 && (nT1&8) != 0;
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IOBit(SRQ1,TSRQ,bNINT2T1 || bNINT2T2);
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2024-03-19 22:24:30 +01:00
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if ((nT1&8) == 0) // timer1 MSB not set
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{
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Chipset.IORam[TIMER1_CTRL] &= ~SRQ; // clear SRQ bit
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return;
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}
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_ASSERT((nT1&8) != 0); // timer1 MSB set
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2024-03-19 23:35:29 +01:00
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// timer MSB and INT or WAKE bit is set
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if ((Chipset.IORam[TIMER1_CTRL]&(WKE|INTR)) != 0)
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2024-03-19 22:24:30 +01:00
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Chipset.IORam[TIMER1_CTRL] |= SRQ; // set SRQ
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// cpu not sleeping and T1 -> Interrupt
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if ( (!Chipset.Shutdn || (Chipset.IORam[TIMER1_CTRL]&WKE))
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&& (Chipset.IORam[TIMER1_CTRL]&INTR))
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{
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Chipset.SoftInt = TRUE;
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bInterrupt = TRUE;
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}
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// cpu sleeping and T1 -> Wake Up
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if (Chipset.Shutdn && (Chipset.IORam[TIMER1_CTRL]&WKE))
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{
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Chipset.IORam[TIMER1_CTRL] &= ~WKE; // clear WKE bit
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2024-03-19 22:25:45 +01:00
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Chipset.bShutdnWake = TRUE; // wake up from SHUTDN mode
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SetEvent(hEventShutdn); // wake up emulation thread
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2024-03-19 22:24:30 +01:00
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}
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return;
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}
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2024-03-19 22:25:45 +01:00
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static VOID CheckT2(DWORD dwT2)
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{
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// implementation of TSRQ
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bNINT2T2 = (Chipset.IORam[TIMER2_CTRL]&INTR) != 0 && (dwT2&0x80000000) != 0;
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IOBit(SRQ1,TSRQ,bNINT2T1 || bNINT2T2);
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2024-03-19 22:24:30 +01:00
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if ((dwT2&0x80000000) == 0) // timer2 MSB not set
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{
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Chipset.IORam[TIMER2_CTRL] &= ~SRQ; // clear SRQ bit
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return;
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}
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_ASSERT((dwT2&0x80000000) != 0); // timer2 MSB set
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2024-03-19 23:35:29 +01:00
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// timer MSB and INT or WAKE bit is set
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if ((Chipset.IORam[TIMER2_CTRL]&(WKE|INTR)) != 0)
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2024-03-19 22:24:30 +01:00
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Chipset.IORam[TIMER2_CTRL] |= SRQ; // set SRQ
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// cpu not sleeping and T2 -> Interrupt
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if ( (!Chipset.Shutdn || (Chipset.IORam[TIMER2_CTRL]&WKE))
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&& (Chipset.IORam[TIMER2_CTRL]&INTR))
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{
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Chipset.SoftInt = TRUE;
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bInterrupt = TRUE;
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}
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// cpu sleeping and T2 -> Wake Up
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if (Chipset.Shutdn && (Chipset.IORam[TIMER2_CTRL]&WKE))
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{
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Chipset.IORam[TIMER2_CTRL] &= ~WKE; // clear WKE bit
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2024-03-19 22:25:45 +01:00
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Chipset.bShutdnWake = TRUE; // wake up from SHUTDN mode
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SetEvent(hEventShutdn); // wake up emulation thread
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2024-03-19 22:24:30 +01:00
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}
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return;
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}
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2024-03-19 22:25:45 +01:00
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static VOID RescheduleT2(BOOL bRefPoint)
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{
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UINT uDelay;
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_ASSERT(uT2TimerId == 0); // timer2 must stopped
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if (bRefPoint) // save reference time
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{
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2024-03-19 22:38:33 +01:00
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dwT2Ref = Chipset.t2; // timer2 value at last timer2 access
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dwT2Cyc = (DWORD) (Chipset.cycles & 0xFFFFFFFF); // cpu cycle counter at last timer2 access
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2024-03-19 22:24:30 +01:00
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QueryPerformanceCounter(&lT2Ref); // time of corresponding Chipset.t2 value
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uDelay = Chipset.t2; // timer value for delay
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}
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else // called without new refpoint, restart t2 with actual value
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{
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uDelay = CalcT2(); // actual timer value for delay
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}
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2024-03-19 23:33:35 +01:00
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if ((bOutRange = uDelay > uT2MaxTicks)) // delay greater maximum delay
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uDelay = uT2MaxTicks; // wait maximum delay time
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uDelay = (uDelay * 125 + 1023) / 1024; // timer delay in ms (1000/8192 = 125/1024)
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uDelay = __max(tc.wPeriodMin,uDelay); // wait minimum delay of timer
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_ASSERT(uDelay <= tc.wPeriodMax); // inside maximum event delay
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// start timer2; schedule event, when Chipset.t2 will be zero
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2024-03-19 23:35:29 +01:00
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VERIFY(uT2TimerId = timeSetEvent(uDelay,0,&TimeProc,2,TIME_ONESHOT));
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return;
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}
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static VOID AbortT2(VOID)
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{
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_ASSERT(uT2TimerId);
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2024-03-19 22:25:45 +01:00
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timeKillEvent(uT2TimerId); // kill event
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uT2TimerId = 0; // then reset var
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2024-03-19 22:24:30 +01:00
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return;
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}
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static void CALLBACK TimeProc(UINT uEventId, UINT uMsg, DWORD dwUser, DWORD dw1, DWORD dw2)
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{
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_ASSERT(uEventId); // illegal EventId
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2024-03-19 22:38:33 +01:00
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2024-03-19 22:25:45 +01:00
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if (uEventId == uT1TimerId) // called from timer1 event (default period 16 Hz)
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{
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2024-03-19 22:25:45 +01:00
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EnterCriticalSection(&csT1Lock);
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2024-03-19 22:24:30 +01:00
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{
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Chipset.t1 = (Chipset.t1-1)&0xF;// decrement timer value
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CheckT1(Chipset.t1); // test timer1 control bits
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}
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2024-03-19 22:25:45 +01:00
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LeaveCriticalSection(&csT1Lock);
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2024-03-19 22:24:30 +01:00
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return;
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}
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2024-03-19 22:25:45 +01:00
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if (uEventId == uT2TimerId) // called from timer2 event, Chipset.t2 should be zero
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2024-03-19 22:24:30 +01:00
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{
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2024-03-19 22:25:45 +01:00
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EnterCriticalSection(&csT2Lock);
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2024-03-19 22:24:30 +01:00
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{
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2024-03-19 22:25:45 +01:00
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uT2TimerId = 0; // single shot timer timer2 stopped
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if (!bOutRange) // timer event elapsed
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2024-03-19 22:24:30 +01:00
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{
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// timer2 overrun, test timer2 control bits else restart timer2
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Chipset.t2 = CalcT2(); // calculate new timer2 value
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CheckT2(Chipset.t2); // test timer2 control bits
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}
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RescheduleT2(!bOutRange); // restart timer2
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}
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2024-03-19 22:25:45 +01:00
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LeaveCriticalSection(&csT2Lock);
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2024-03-19 22:24:30 +01:00
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return;
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}
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return;
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UNREFERENCED_PARAMETER(uMsg);
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2024-03-19 22:25:45 +01:00
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UNREFERENCED_PARAMETER(dwUser);
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2024-03-19 22:24:30 +01:00
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UNREFERENCED_PARAMETER(dw1);
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UNREFERENCED_PARAMETER(dw2);
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}
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2024-03-19 22:25:45 +01:00
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VOID SetHP48Time(VOID) // set date and time
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{
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SYSTEMTIME ts;
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2024-03-19 22:38:33 +01:00
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ULONGLONG ticks, time;
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2024-03-19 22:25:45 +01:00
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DWORD dw;
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WORD crc, i;
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BYTE p[4];
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2024-03-19 22:38:33 +01:00
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_ASSERT(sizeof(ULONGLONG) == 8); // check size of datatype
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2024-03-19 22:25:45 +01:00
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GetLocalTime(&ts); // local time, _ftime() cause memory/resource leaks
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// calculate days until 01.01.1970
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dw = (DWORD) ts.wMonth;
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if (dw > 2)
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dw -= 3L;
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else
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{
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dw += 9L;
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--ts.wYear;
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}
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dw = (DWORD) ts.wDay + (153L * dw + 2L) / 5L;
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dw += (146097L * (((DWORD) ts.wYear) / 100L)) / 4L;
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dw += (1461L * (((DWORD) ts.wYear) % 100L)) / 4L;
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dw -= 719469L;
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// convert into seconds and add time
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dw = dw * 24L + (DWORD) ts.wHour;
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dw = dw * 60L + (DWORD) ts.wMinute;
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dw = dw * 60L + (DWORD) ts.wSecond;
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// create timerticks = (s + ms) * 8192
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2024-03-19 22:38:33 +01:00
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ticks = ((ULONGLONG) dw << 13) | (((ULONGLONG) ts.wMilliseconds << 10) / 125);
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2024-03-19 22:25:45 +01:00
|
|
|
|
|
|
|
ticks += UNIX_0_TIME; // add offset ticks from year 0
|
2024-03-19 22:38:33 +01:00
|
|
|
ticks += Chipset.t2; // add actual timer2 value
|
2024-03-19 22:25:45 +01:00
|
|
|
|
|
|
|
time = ticks; // save for calc. timeout
|
|
|
|
time += OFF_TIME; // add 10 min for auto off
|
|
|
|
|
|
|
|
dw = RPLTIME; // HP addresses for clock in port0
|
|
|
|
|
|
|
|
crc = 0x0; // reset crc value
|
|
|
|
for (i = 0; i < 13; ++i, ++dw) // write date and time
|
|
|
|
{
|
|
|
|
*p = (BYTE) ticks & 0xf;
|
|
|
|
crc = (crc >> 4) ^ (((crc ^ ((WORD) *p)) & 0xf) * 0x1081);
|
|
|
|
Chipset.Port0[dw] = *p; // always store in port0
|
|
|
|
ticks >>= 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
Nunpack(p,crc,4); // write crc
|
|
|
|
memcpy(Chipset.Port0+dw,p,4); // always store in port0
|
|
|
|
|
|
|
|
dw += 4; // HP addresses for timeout
|
|
|
|
|
|
|
|
for (i = 0; i < 13; ++i, ++dw) // write time for auto off
|
|
|
|
{
|
|
|
|
// always store in port0
|
|
|
|
Chipset.Port0[dw] = (BYTE) time & 0xf;
|
|
|
|
time >>= 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
Chipset.Port0[dw] = 0xf; // always store in port0
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2024-03-19 22:24:30 +01:00
|
|
|
VOID StartTimers(VOID)
|
|
|
|
{
|
|
|
|
if (bStarted) // timer running
|
|
|
|
return; // -> quit
|
|
|
|
if (Chipset.IORam[TIMER2_CTRL]&RUN) // start timer1 and timer2 ?
|
|
|
|
{
|
|
|
|
bStarted = TRUE; // flag timer running
|
2024-03-19 22:36:03 +01:00
|
|
|
// initialisation of NINT2 lines
|
2024-03-19 22:25:45 +01:00
|
|
|
bNINT2T1 = (Chipset.IORam[TIMER1_CTRL]&INTR) != 0 && (Chipset.t1 & 8) != 0;
|
|
|
|
bNINT2T2 = (Chipset.IORam[TIMER2_CTRL]&INTR) != 0 && (Chipset.t2 & 0x80000000) != 0;
|
|
|
|
timeGetDevCaps(&tc,sizeof(tc)); // get timer resolution
|
2024-03-19 23:33:35 +01:00
|
|
|
|
|
|
|
// max. timer2 ticks that can be handled by one timer event
|
|
|
|
uT2MaxTicks = __min((0xFFFFFFFF / 1024),tc.wPeriodMax);
|
|
|
|
uT2MaxTicks = __min((0xFFFFFFFF - 1023) / 125,uT2MaxTicks * 1024 / 125);
|
|
|
|
|
2024-03-19 22:37:03 +01:00
|
|
|
CheckT1(Chipset.t1); // check for timer1 interrupts
|
|
|
|
CheckT2(Chipset.t2); // check for timer2 interrupts
|
2024-03-19 23:33:35 +01:00
|
|
|
// set timer resolution to greatest possible one
|
|
|
|
bAccurateTimer = (timeBeginPeriod(tc.wPeriodMin) == TIMERR_NOERROR);
|
2024-03-19 22:24:30 +01:00
|
|
|
// set timer1 with given period
|
2024-03-19 23:35:29 +01:00
|
|
|
VERIFY(uT1TimerId = timeSetEvent(T1_FREQ,0,&TimeProc,1,TIME_PERIODIC));
|
2024-03-19 22:24:30 +01:00
|
|
|
RescheduleT2(TRUE); // start timer2
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
VOID StopTimers(VOID)
|
|
|
|
{
|
|
|
|
if (!bStarted) // timer stopped
|
|
|
|
return; // -> quit
|
|
|
|
if (uT1TimerId != 0) // timer1 running
|
|
|
|
{
|
2024-03-19 22:25:45 +01:00
|
|
|
// Critical Section handler may cause a dead lock
|
2024-03-19 22:24:30 +01:00
|
|
|
timeKillEvent(uT1TimerId); // stop timer1
|
|
|
|
uT1TimerId = 0; // set flag timer1 stopped
|
|
|
|
}
|
|
|
|
if (uT2TimerId != 0) // timer2 running
|
|
|
|
{
|
2024-03-19 22:25:45 +01:00
|
|
|
EnterCriticalSection(&csT2Lock);
|
2024-03-19 22:24:30 +01:00
|
|
|
{
|
2024-03-19 22:25:45 +01:00
|
|
|
Chipset.t2 = CalcT2(); // update chipset timer2 value
|
2024-03-19 22:24:30 +01:00
|
|
|
}
|
2024-03-19 22:25:45 +01:00
|
|
|
LeaveCriticalSection(&csT2Lock);
|
2024-03-19 22:37:54 +01:00
|
|
|
AbortT2(); // stop timer2 outside critical section
|
2024-03-19 22:24:30 +01:00
|
|
|
}
|
|
|
|
bStarted = FALSE;
|
|
|
|
if (bAccurateTimer) // "Accurate timer" running
|
|
|
|
{
|
2024-03-19 23:33:35 +01:00
|
|
|
timeEndPeriod(tc.wPeriodMin); // finish service
|
2024-03-19 22:24:30 +01:00
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
DWORD ReadT2(VOID)
|
|
|
|
{
|
|
|
|
DWORD dwT2;
|
|
|
|
EnterCriticalSection(&csT2Lock);
|
|
|
|
{
|
2024-03-19 22:38:33 +01:00
|
|
|
dwT2 = CalcT2(); // calculate timer2 value or if stopped last timer value
|
2024-03-19 22:25:45 +01:00
|
|
|
CheckT2(dwT2); // update timer2 control bits
|
2024-03-19 22:24:30 +01:00
|
|
|
}
|
|
|
|
LeaveCriticalSection(&csT2Lock);
|
|
|
|
return dwT2;
|
|
|
|
}
|
|
|
|
|
|
|
|
VOID SetT2(DWORD dwValue)
|
|
|
|
{
|
|
|
|
// calling AbortT2() inside Critical Section handler may cause a dead lock
|
2024-03-19 22:25:45 +01:00
|
|
|
if (uT2TimerId != 0) // timer2 running
|
|
|
|
AbortT2(); // stop timer2
|
2024-03-19 22:24:30 +01:00
|
|
|
EnterCriticalSection(&csT2Lock);
|
|
|
|
{
|
|
|
|
Chipset.t2 = dwValue; // set new value
|
2024-03-19 22:25:45 +01:00
|
|
|
CheckT2(Chipset.t2); // test timer2 control bits
|
2024-03-19 22:24:30 +01:00
|
|
|
if (bStarted) // timer running
|
|
|
|
RescheduleT2(TRUE); // restart timer2
|
|
|
|
}
|
|
|
|
LeaveCriticalSection(&csT2Lock);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
BYTE ReadT1(VOID)
|
|
|
|
{
|
|
|
|
BYTE nT1;
|
2024-03-19 22:25:45 +01:00
|
|
|
EnterCriticalSection(&csT1Lock);
|
2024-03-19 22:24:30 +01:00
|
|
|
{
|
|
|
|
nT1 = Chipset.t1; // read timer1 value
|
2024-03-19 22:25:45 +01:00
|
|
|
CheckT1(nT1); // update timer1 control bits
|
2024-03-19 22:24:30 +01:00
|
|
|
}
|
2024-03-19 22:25:45 +01:00
|
|
|
LeaveCriticalSection(&csT1Lock);
|
2024-03-19 22:24:30 +01:00
|
|
|
return nT1;
|
|
|
|
}
|
|
|
|
|
|
|
|
VOID SetT1(BYTE byValue)
|
|
|
|
{
|
2024-03-19 23:35:29 +01:00
|
|
|
BOOL bEqual;
|
|
|
|
|
2024-03-19 22:25:45 +01:00
|
|
|
_ASSERT(byValue < 0x10); // timer1 is only a 4bit counter
|
|
|
|
|
2024-03-19 23:35:29 +01:00
|
|
|
EnterCriticalSection(&csT1Lock);
|
|
|
|
{
|
|
|
|
bEqual = (Chipset.t1 == byValue); // check for same value
|
|
|
|
}
|
|
|
|
LeaveCriticalSection(&csT1Lock);
|
|
|
|
if (bEqual) return; // same value doesn't restart timer period
|
2024-03-19 22:25:45 +01:00
|
|
|
|
2024-03-19 23:35:29 +01:00
|
|
|
if (uT1TimerId != 0) // timer1 running
|
|
|
|
{
|
|
|
|
timeKillEvent(uT1TimerId); // stop timer1
|
|
|
|
uT1TimerId = 0; // set flag timer1 stopped
|
|
|
|
}
|
2024-03-19 22:25:45 +01:00
|
|
|
EnterCriticalSection(&csT1Lock);
|
2024-03-19 22:24:30 +01:00
|
|
|
{
|
2024-03-19 22:25:45 +01:00
|
|
|
Chipset.t1 = byValue; // set new timer1 value
|
|
|
|
CheckT1(Chipset.t1); // test timer1 control bits
|
2024-03-19 22:24:30 +01:00
|
|
|
}
|
2024-03-19 22:25:45 +01:00
|
|
|
LeaveCriticalSection(&csT1Lock);
|
2024-03-19 23:35:29 +01:00
|
|
|
if (bStarted) // timer running
|
|
|
|
{
|
|
|
|
// restart timer1 to get full period of frequency
|
|
|
|
VERIFY(uT1TimerId = timeSetEvent(T1_FREQ,0,&TimeProc,1,TIME_PERIODIC));
|
|
|
|
}
|
2024-03-19 22:24:30 +01:00
|
|
|
return;
|
|
|
|
}
|