2024-03-19 22:24:30 +01:00
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/*
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* engine.c
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*
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* This file is part of Emu48
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*
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* Copyright (C) 1995 Sebastien Carlier
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*
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*/
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#include "pch.h"
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#include "Emu48.h"
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2024-03-19 22:25:45 +01:00
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#include "Opcodes.h"
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2024-03-19 22:36:03 +01:00
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#include "io.h"
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2024-03-19 22:25:45 +01:00
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#include "debugger.h"
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2024-03-19 22:24:30 +01:00
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2024-03-19 22:25:45 +01:00
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#define SAMPLE 16384 // speed adjust sample frequency
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2024-03-19 22:25:45 +01:00
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BOOL bInterrupt = FALSE;
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UINT nState = 1;
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UINT nNextState = 0;
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BOOL bRealSpeed = FALSE;
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2024-03-19 22:25:45 +01:00
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BOOL bKeySlow = FALSE; // slow down for key emulation
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CHIPSET Chipset;
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2024-03-19 22:25:45 +01:00
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char szSerialWire[16]; // evicename for wire port
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char szSerialIr[16]; // devicename for IR port
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2024-03-19 22:25:45 +01:00
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DWORD dwSXCycles = 82; // SX cpu cycles in interval
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DWORD dwGXCycles = 123; // GX cpu cycles in interval
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static BOOL bCommInit = FALSE; // COM port not open
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2024-03-19 22:36:03 +01:00
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static BOOL bCpuSlow = FALSE; // enable/disable real speed
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static DWORD dwEDbgT2 = 0; // debugger timer2 emulation
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static DWORD dwEDbgCycles = 0; // debugger cycle counter
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static DWORD dwOldCyc; // cpu cycles at last event
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static DWORD dwSpeedRef; // timer value at last event
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static DWORD dwTickRef; // sample timer ticks
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#include "Ops.h"
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2024-03-19 22:36:03 +01:00
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// save last instruction in circular instruction buffer
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static __inline VOID SaveInstrAddr(DWORD dwAddr)
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{
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if (pdwInstrArray) // circular buffer allocated
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{
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pdwInstrArray[wInstrWp] = dwAddr;
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wInstrWp = (wInstrWp + 1) % wInstrSize;
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if (wInstrWp == wInstrRp)
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wInstrRp = (wInstrRp + 1) % wInstrSize;
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}
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return;
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}
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static __inline VOID Debugger(VOID) // debugger part
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{
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LARGE_INTEGER lDummyInt; // sample timer ticks
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BOOL bStopEmulation;
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BOOL bRplBreak = FALSE; // flag for RPL breakpoint
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LPBYTE I = FASTPTR(Chipset.pc); // get opcode stream
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SaveInstrAddr(Chipset.pc); // save pc in last instruction buffer
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// check for code breakpoints
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bStopEmulation = CheckBreakpoint(Chipset.pc, 1, BP_EXEC);
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// check for memory breakpoints, opcode #14x or #15x
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if (I[0] == 0x1 && (I[1] == 0x4 || I[1] == 0x5))
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{
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DWORD dwData = (I[2] & 0x1) ? Chipset.d1 : Chipset.d0;
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UINT nType = (I[2] & 0x2) ? BP_READ : BP_WRITE;
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DWORD dwRange;
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if (I[1] == 0x4) // B,A
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{
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dwRange = (I[2] & 0x8) ? 2 : 5;
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}
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else // P,WP,XS,X,S,M,W or number of nibbles
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{
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if (I[2] & 0x8) // number of nibbles
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{
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dwRange = I[3]+1;
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}
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else // P,WP,XS,X,S,M,W
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{
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dwData += F_s[I[3]];
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dwRange = F_l[I[3]];
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}
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}
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#if defined DEBUG_DEBUGGER
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{
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char buffer[256];
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wsprintf(buffer,"Memory breakpoint %.5lx, %u\n",dwData,dwRange);
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OutputDebugString(buffer);
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}
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#endif
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bStopEmulation |= CheckBreakpoint(dwData, dwRange, nType);
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}
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// NOP3, opcode #420 (GOC)
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if (bDbgNOP3 && I[0] == 0x4 && I[1] == 0x2 && I[2] == 0x0)
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bStopEmulation = TRUE;
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// RPL breakpoints, PC=(A), opcode #808C or PC=(C), opcode #808E
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if (bDbgRPL && I[0] == 0x8 && I[1] == 0x0 && I[2] == 0x8 && (I[3] == 0xC || I[3] == 0xE ))
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{
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BYTE byRplPtr[5];
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// A=DAT0 A, D0=D0+ 5, PC=(A)
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// C=DAT0 A, D0=D0+ 5, PC=(C)
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Npeek(byRplPtr,Chipset.d0-5,5);
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if (memcmp(byRplPtr,(I[3] == 0xC) ? Chipset.A : Chipset.C,5) == 0)
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{
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bRplBreak = TRUE;
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bStopEmulation = TRUE;
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}
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}
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// step over interrupt execution
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if (bDbgSkipInt && !bStopEmulation && !Chipset.inte)
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return;
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// check for step into
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bStopEmulation |= (nDbgState == DBG_STEPINTO);
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// check for step over
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bStopEmulation |= (nDbgState == DBG_STEPOVER) && dwDbgRstkp == Chipset.rstkp;
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// check for step out, something was popped from hardware stack
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if (nDbgState == DBG_STEPOUT && dwDbgRstkp == Chipset.rstkp)
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{
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_ASSERT(bStopEmulation == FALSE);
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if ((bStopEmulation = (Chipset.pc == dwDbgRstk)) == FALSE)
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{
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// it was C=RSTK, check for next object popped from hardware stack
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dwDbgRstkp = (Chipset.rstkp-1)&7;
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dwDbgRstk = Chipset.rstk[dwDbgRstkp];
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}
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}
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if (bStopEmulation) // stop condition
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{
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StopTimers(); // hold timer values when emulator is stopped
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if (Chipset.IORam[TIMER2_CTRL]&RUN) // check if timer running
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{
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if (dwEDbgT2 == Chipset.t2)
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{
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// cpu cycles for one timer2 tick elapsed
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if ((DWORD) (Chipset.cycles & 0xFFFFFFFF) - dwEDbgCycles
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>= (SAMPLE / 8192) * (DWORD) T2CYCLES)
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{
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--Chipset.t2;
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// adjust cycles reference
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dwEDbgCycles += (SAMPLE / 8192) * T2CYCLES;
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}
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}
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else // new timer2 value
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{
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// new cycle reference
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dwEDbgCycles = (DWORD) (Chipset.cycles & 0xFFFFFFFF);
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}
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// check rising edge of Bit 8 of timer2
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if ((dwEDbgT2 & 0x100) == 0 && (Chipset.t2 & 0x100) != 0)
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Chipset.t1 = (Chipset.t1 - 1) & 0xF;
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}
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dwEDbgT2 = Chipset.t2; // timer2 check reference value
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// OutputDebugString("Emulator stopped...\n");
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NotifyDebugger(bRplBreak);
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WaitForSingleObject(hEventDebug,INFINITE);
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// OutputDebugString("Emulator running...\n");
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StartTimers(); // continue timers
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Chipset.Shutdn = FALSE;
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Chipset.bShutdnWake = FALSE;
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// init slow down part
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dwOldCyc = (DWORD) (Chipset.cycles & 0xFFFFFFFF);
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QueryPerformanceCounter(&lDummyInt);
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dwSpeedRef = lDummyInt.LowPart;
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}
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}
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2024-03-19 22:25:45 +01:00
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static __inline VOID CheckDisp(BOOL bSync)
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{
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if (disp == 0) return; // no display update need
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// update display when drawing top line or display is off
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if (bSync && GetLineCounter() != 0x3F && (Chipset.IORam[0x00]&8))
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return;
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2024-03-19 22:25:45 +01:00
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_ASSERT((disp & DISP_POINTER) == 0); // display pointer already updated
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if (disp & DISP_MAIN) UpdateMainDisplay();
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if (disp & DISP_MENUE) UpdateMenuDisplay();
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_ASSERT((disp & DISP_ANNUN) == 0); // annunciators already updated
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disp = 0; // display updated
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return;
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}
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static __inline VOID CheckSerial(VOID)
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{
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if (ioc_acc) // IOC changed
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{
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ioc_acc = FALSE;
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// COM port closed and serial on
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if (bCommInit == FALSE && (Chipset.IORam[IOC] & SON) != 0)
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{
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CommOpen(szSerialWire,szSerialIr); // open COM ports
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bCommInit = CommConnect() != PORT_CLOSE;
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}
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// COM port opend and serial off
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if (bCommInit == TRUE && (Chipset.IORam[IOC] & SON) == 0)
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{
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CommClose(); // close COM port
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bCommInit = FALSE;
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}
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// Interrupt on recv buffer full and receive buffer full
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if ((Chipset.IORam[IOC] & ERBF) && (Chipset.IORam[RCS] & RBF))
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{
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Chipset.Shutdn = FALSE;
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INTERRUPT;
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}
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}
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}
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static __inline VOID AdjustSpeed(VOID) // adjust emulation speed
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{
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if (bCpuSlow || bKeySlow) // emulation slow down
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{
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DWORD dwCycles,dwTicks;
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2024-03-19 22:24:30 +01:00
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// cycles elapsed for next check
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if ((dwCycles = (DWORD) (Chipset.cycles & 0xFFFFFFFF)-dwOldCyc) >= (DWORD) T2CYCLES)
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{
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LARGE_INTEGER lAct;
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do
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{
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BOOL bErr = QueryPerformanceCounter(&lAct);
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_ASSERT(bErr); // no high-resolution performance counter
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}
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2024-03-19 22:36:03 +01:00
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while((dwTicks = lAct.LowPart-dwSpeedRef) <= dwTickRef);
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2024-03-19 22:36:03 +01:00
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// workaround for QueryPerformanceCounter() in Win2k,
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// if last command sequence took over 50ms -> synchronize
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if(dwTicks > 819 * dwTickRef) // time for last commands > 50ms (819 / 16384Hz)
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{
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// new synchronizing
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dwOldCyc = (DWORD) (Chipset.cycles & 0xFFFFFFFF);
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QueryPerformanceCounter(&lAct); // get timer ticks
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dwSpeedRef = lAct.LowPart; // save reference time
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}
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else
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{
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dwOldCyc += T2CYCLES; // adjust cycles reference
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dwSpeedRef += dwTickRef; // adjust reference time
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}
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2024-03-19 22:24:30 +01:00
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}
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}
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return;
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}
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2024-03-19 22:25:45 +01:00
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VOID AdjKeySpeed(VOID) // slow down key repeat
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2024-03-19 22:24:30 +01:00
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{
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WORD i;
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BOOL bKey;
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2024-03-19 22:36:03 +01:00
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if (bCpuSlow) return; // no need to slow down
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2024-03-19 22:24:30 +01:00
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bKey = FALSE; // search for a pressed key
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for (i = 0;i < sizeof(Chipset.Keyboard_Row) / sizeof(Chipset.Keyboard_Row[0]) && !bKey;++i)
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bKey = (Chipset.Keyboard_Row[i] != 0);
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if (!bKeySlow && bKey) // key pressed, init variables
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{
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LARGE_INTEGER lTime; // sample timer ticks
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2024-03-19 22:25:45 +01:00
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// save reference cycles
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dwOldCyc = (DWORD) (Chipset.cycles & 0xFFFFFFFF);
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2024-03-19 22:24:30 +01:00
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QueryPerformanceCounter(&lTime); // get timer ticks
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dwSpeedRef = lTime.LowPart; // save reference time
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}
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bKeySlow = bKey; // save new state
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return;
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}
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2024-03-19 22:25:45 +01:00
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VOID SetSpeed(BOOL bAdjust) // set emulation speed
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2024-03-19 22:24:30 +01:00
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{
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2024-03-19 22:25:45 +01:00
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if (bAdjust) // switch to real speed
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{
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LARGE_INTEGER lTime; // sample timer ticks
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2024-03-19 22:25:45 +01:00
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// save reference cycles
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dwOldCyc = (DWORD) (Chipset.cycles & 0xFFFFFFFF);
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2024-03-19 22:24:30 +01:00
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QueryPerformanceCounter(&lTime); // get timer ticks
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dwSpeedRef = lTime.LowPart; // save reference time
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}
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2024-03-19 22:36:03 +01:00
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bCpuSlow = bAdjust; // save emulation speed
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2024-03-19 22:24:30 +01:00
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}
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2024-03-19 22:25:45 +01:00
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VOID UpdateKdnBit(VOID) // update KDN bit
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2024-03-19 22:24:30 +01:00
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{
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2024-03-19 22:25:45 +01:00
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if (Chipset.intk && (DWORD) (Chipset.cycles & 0xFFFFFFFFF) - Chipset.dwKdnCycles > (DWORD) T2CYCLES * 16)
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IOBit(0x19,8,Chipset.in != 0);
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}
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2024-03-19 22:25:45 +01:00
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BOOL WaitForSleepState(VOID) // wait for cpu SHUTDN then sleep state
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2024-03-19 22:24:30 +01:00
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{
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DWORD dwRefTime = timeGetTime();
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// wait for the SHUTDN command with 1.5 sec timeout
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while (timeGetTime() - dwRefTime < 1500L && !Chipset.Shutdn)
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Sleep(0);
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|
|
|
|
if (Chipset.Shutdn) // not timeout, cpu is down
|
|
|
|
SwitchToState(3); // go to sleep state
|
|
|
|
|
|
|
|
return 3 != nNextState; // state not changed, emulator was busy
|
|
|
|
}
|
|
|
|
|
|
|
|
UINT SwitchToState(UINT nNewState)
|
|
|
|
{
|
|
|
|
UINT nOldState = nState;
|
|
|
|
|
|
|
|
if (nState == nNewState) return nOldState;
|
|
|
|
switch (nState)
|
|
|
|
{
|
|
|
|
case 0: // Run
|
2024-03-19 22:25:45 +01:00
|
|
|
if (hDlgDebug) // debugger running
|
|
|
|
{
|
|
|
|
DestroyWindow(hDlgDebug); // then close debugger to renter emulation
|
|
|
|
hDlgDebug = NULL;
|
|
|
|
}
|
2024-03-19 22:24:30 +01:00
|
|
|
switch (nNewState)
|
|
|
|
{
|
|
|
|
case 1: // -> Invalid
|
|
|
|
nNextState = 1;
|
|
|
|
if (Chipset.Shutdn)
|
2024-03-19 22:25:45 +01:00
|
|
|
SetEvent(hEventShutdn);
|
2024-03-19 22:24:30 +01:00
|
|
|
else
|
|
|
|
bInterrupt = TRUE;
|
|
|
|
while (nState!=nNextState) Sleep(0);
|
|
|
|
UpdateWindowStatus();
|
|
|
|
break;
|
|
|
|
case 2: // -> Return
|
|
|
|
nNextState = 1;
|
|
|
|
if (Chipset.Shutdn)
|
2024-03-19 22:25:45 +01:00
|
|
|
SetEvent(hEventShutdn);
|
2024-03-19 22:24:30 +01:00
|
|
|
else
|
|
|
|
bInterrupt = TRUE;
|
|
|
|
while (nState!=nNextState) Sleep(0);
|
|
|
|
nNextState = 2;
|
2024-03-19 22:25:45 +01:00
|
|
|
SetEvent(hEventShutdn);
|
2024-03-19 22:24:30 +01:00
|
|
|
while (nState!=nNextState) Sleep(0);
|
|
|
|
UpdateWindowStatus();
|
|
|
|
break;
|
|
|
|
case 3: // -> Sleep
|
|
|
|
nNextState = 3;
|
|
|
|
if (Chipset.Shutdn)
|
2024-03-19 22:25:45 +01:00
|
|
|
SetEvent(hEventShutdn);
|
2024-03-19 22:24:30 +01:00
|
|
|
else
|
|
|
|
bInterrupt = TRUE;
|
|
|
|
while (nState!=nNextState) Sleep(0);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1: // Invalid
|
|
|
|
switch (nNewState)
|
|
|
|
{
|
|
|
|
case 0: // -> Run
|
|
|
|
nNextState = 0;
|
2024-03-19 22:36:03 +01:00
|
|
|
// don't enter opcode loop on interrupt request
|
|
|
|
bInterrupt = Chipset.Shutdn || Chipset.SoftInt;
|
2024-03-19 22:25:45 +01:00
|
|
|
SetEvent(hEventShutdn);
|
2024-03-19 22:24:30 +01:00
|
|
|
while (nState!=nNextState) Sleep(0);
|
|
|
|
UpdateWindowStatus();
|
|
|
|
break;
|
|
|
|
case 2: // -> Return
|
|
|
|
nNextState = 2;
|
2024-03-19 22:25:45 +01:00
|
|
|
SetEvent(hEventShutdn);
|
2024-03-19 22:24:30 +01:00
|
|
|
while (nState!=nNextState) Sleep(0);
|
|
|
|
break;
|
|
|
|
case 3: // -> Sleep
|
|
|
|
nNextState = 3;
|
2024-03-19 22:25:45 +01:00
|
|
|
SetEvent(hEventShutdn);
|
2024-03-19 22:24:30 +01:00
|
|
|
while (nState!=nNextState) Sleep(0);
|
|
|
|
UpdateWindowStatus();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 3: // Sleep
|
|
|
|
switch (nNewState)
|
|
|
|
{
|
|
|
|
case 0: // -> Run
|
|
|
|
nNextState = 0;
|
|
|
|
if (Chipset.Shutdn) bInterrupt=TRUE;
|
2024-03-19 22:25:45 +01:00
|
|
|
SetEvent(hEventShutdn);
|
2024-03-19 22:24:30 +01:00
|
|
|
break;
|
|
|
|
case 1: // -> Invalid
|
|
|
|
nNextState = 1;
|
2024-03-19 22:25:45 +01:00
|
|
|
SetEvent(hEventShutdn);
|
2024-03-19 22:24:30 +01:00
|
|
|
while (nState!=nNextState) Sleep(0);
|
|
|
|
UpdateWindowStatus();
|
|
|
|
break;
|
|
|
|
case 2: // -> Return
|
|
|
|
nNextState = 1;
|
2024-03-19 22:25:45 +01:00
|
|
|
SetEvent(hEventShutdn);
|
2024-03-19 22:24:30 +01:00
|
|
|
while (nState!=nNextState) Sleep(0);
|
|
|
|
nNextState = 2;
|
2024-03-19 22:25:45 +01:00
|
|
|
SetEvent(hEventShutdn);
|
2024-03-19 22:24:30 +01:00
|
|
|
while (nState!=nNextState) Sleep(0);
|
|
|
|
UpdateWindowStatus();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return nOldState;
|
|
|
|
}
|
|
|
|
|
|
|
|
UINT WorkerThread(LPVOID pParam)
|
|
|
|
{
|
2024-03-19 22:25:45 +01:00
|
|
|
LARGE_INTEGER lDummyInt; // sample timer ticks
|
|
|
|
QueryPerformanceFrequency(&lDummyInt); // init timer ticks
|
|
|
|
lDummyInt.QuadPart /= SAMPLE; // calculate sample ticks
|
|
|
|
dwTickRef = lDummyInt.LowPart; // sample timer ticks
|
|
|
|
_ASSERT(dwTickRef); // tick resolution error
|
2024-03-19 22:24:30 +01:00
|
|
|
|
|
|
|
loop:
|
|
|
|
while (nNextState == 1) // go into invalid state
|
|
|
|
{
|
2024-03-19 22:25:45 +01:00
|
|
|
CommClose(); // close COM port
|
|
|
|
bCommInit = FALSE; // COM port not open
|
2024-03-19 22:24:30 +01:00
|
|
|
nState = 1; // in invalid state
|
2024-03-19 22:25:45 +01:00
|
|
|
WaitForSingleObject(hEventShutdn,INFINITE);
|
2024-03-19 22:24:30 +01:00
|
|
|
if (nNextState == 2) // go into return state
|
|
|
|
{
|
|
|
|
nState = 2; // in return state
|
|
|
|
return 0; // kill thread
|
|
|
|
}
|
2024-03-19 22:25:45 +01:00
|
|
|
ioc_acc = TRUE; // test if UART on
|
2024-03-19 22:24:30 +01:00
|
|
|
}
|
|
|
|
while (nNextState == 0)
|
|
|
|
{
|
|
|
|
if (nState!=0)
|
|
|
|
{
|
|
|
|
nState = 0;
|
2024-03-19 22:25:45 +01:00
|
|
|
// clear port2 status bits
|
|
|
|
Chipset.cards_status &= ~(PORT2_PRESENT | PORT2_WRITE);
|
|
|
|
if (pbyPort2 || Chipset.Port2) // card plugged in port2
|
2024-03-19 22:24:30 +01:00
|
|
|
{
|
2024-03-19 22:25:45 +01:00
|
|
|
Chipset.cards_status |= PORT2_PRESENT;
|
|
|
|
|
|
|
|
if (bPort2Writeable) // is card writeable
|
|
|
|
Chipset.cards_status |= PORT2_WRITE;
|
2024-03-19 22:24:30 +01:00
|
|
|
}
|
2024-03-19 22:36:03 +01:00
|
|
|
// card detection off and timer running
|
|
|
|
if ((Chipset.IORam[CARDCTL] & ECDT) == 0 && (Chipset.IORam[TIMER2_CTRL] & RUN) != 0)
|
|
|
|
{
|
|
|
|
BOOL bNINT2 = Chipset.IORam[SRQ1] == 0 && (Chipset.IORam[SRQ2] & LSRQ) == 0;
|
|
|
|
BOOL bNINT = (Chipset.IORam[CARDCTL] & SMP) == 0;
|
|
|
|
|
|
|
|
// state of CDT2
|
|
|
|
bNINT2 = bNINT2 && (Chipset.cards_status & (P2W|P2C)) != P2C;
|
|
|
|
// state of CDT1
|
|
|
|
bNINT = bNINT && (Chipset.cards_status & (P1W|P1C)) != P1C;
|
|
|
|
|
|
|
|
IOBit(SRQ2,NINT2,bNINT2);
|
|
|
|
IOBit(SRQ2,NINT,bNINT);
|
|
|
|
}
|
2024-03-19 22:25:45 +01:00
|
|
|
RomSwitch(Chipset.Bank_FF); // select HP49G ROM bank and update memory mapping
|
2024-03-19 22:24:30 +01:00
|
|
|
UpdateDisplayPointers();
|
|
|
|
UpdateMainDisplay();
|
|
|
|
UpdateMenuDisplay();
|
|
|
|
UpdateAnnunciators();
|
2024-03-19 22:25:45 +01:00
|
|
|
// init speed reference
|
|
|
|
dwOldCyc = (DWORD) (Chipset.cycles & 0xFFFFFFFF);
|
2024-03-19 22:24:30 +01:00
|
|
|
QueryPerformanceCounter(&lDummyInt);
|
|
|
|
dwSpeedRef = lDummyInt.LowPart;
|
2024-03-19 22:25:45 +01:00
|
|
|
SetHP48Time(); // update HP48 time & date
|
2024-03-19 22:24:30 +01:00
|
|
|
StartTimers();
|
|
|
|
}
|
|
|
|
PCHANGED;
|
|
|
|
while (!bInterrupt)
|
|
|
|
{
|
2024-03-19 22:36:03 +01:00
|
|
|
if (bDbgEnable) Debugger(); // debugger active
|
2024-03-19 22:25:45 +01:00
|
|
|
|
2024-03-19 22:36:03 +01:00
|
|
|
EvalOpcode(FASTPTR(Chipset.pc)); // execute opcode
|
2024-03-19 22:25:45 +01:00
|
|
|
|
|
|
|
CheckDisp(!Chipset.Shutdn); // check for display update
|
|
|
|
CheckSerial(); // serial support
|
|
|
|
AdjustSpeed(); // adjust emulation speed
|
2024-03-19 22:24:30 +01:00
|
|
|
}
|
2024-03-19 22:25:45 +01:00
|
|
|
bInterrupt = FALSE; // be sure to reenter opcode loop
|
|
|
|
|
|
|
|
// enter SHUTDN handler only in RUN mode
|
|
|
|
if (Chipset.Shutdn && !(nDbgState == DBG_STEPINTO || nDbgState == DBG_STEPOVER))
|
2024-03-19 22:24:30 +01:00
|
|
|
{
|
2024-03-19 22:36:03 +01:00
|
|
|
if (!Chipset.SoftInt) // ignore SHUTDN on interrupt request
|
|
|
|
WaitForSingleObject(hEventShutdn,INFINITE);
|
|
|
|
else
|
|
|
|
Chipset.bShutdnWake = TRUE; // waked by interrupt
|
2024-03-19 22:25:45 +01:00
|
|
|
|
|
|
|
if (Chipset.bShutdnWake) // waked up by timer, keyboard or serial
|
|
|
|
{
|
|
|
|
Chipset.bShutdnWake = FALSE;
|
|
|
|
Chipset.Shutdn = FALSE;
|
|
|
|
// init speed reference
|
|
|
|
dwOldCyc = (DWORD) (Chipset.cycles & 0xFFFFFFFF);
|
|
|
|
QueryPerformanceCounter(&lDummyInt);
|
|
|
|
dwSpeedRef = lDummyInt.LowPart;
|
|
|
|
}
|
2024-03-19 22:24:30 +01:00
|
|
|
}
|
|
|
|
if (Chipset.SoftInt)
|
|
|
|
{
|
|
|
|
Chipset.SoftInt = FALSE;
|
|
|
|
if (Chipset.inte)
|
|
|
|
{
|
|
|
|
Chipset.inte = FALSE;
|
|
|
|
rstkpush(Chipset.pc);
|
|
|
|
Chipset.pc = 0xf;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2024-03-19 22:36:03 +01:00
|
|
|
_ASSERT(nNextState != 0);
|
|
|
|
|
|
|
|
StopTimers();
|
|
|
|
|
2024-03-19 22:24:30 +01:00
|
|
|
while (nNextState == 3) // go into sleep state
|
|
|
|
{
|
|
|
|
nState = 3; // in sleep state
|
2024-03-19 22:25:45 +01:00
|
|
|
WaitForSingleObject(hEventShutdn,INFINITE);
|
2024-03-19 22:24:30 +01:00
|
|
|
}
|
|
|
|
goto loop;
|
|
|
|
UNREFERENCED_PARAMETER(pParam);
|
|
|
|
}
|