x49gp/qemu/patches/qemu-0.9.0-sparc-load-store-le.patch

67 lines
2 KiB
Diff

diff -ur qemu/cpu-all.h qemu-0.9.0/cpu-all.h
--- qemu/cpu-all.h 2007-07-21 11:53:24.000000000 +0200
+++ qemu-0.9.0/cpu-all.h 2007-07-04 09:48:06.000000000 +0200
@@ -24,6 +24,12 @@
#define WORDS_ALIGNED
#endif
+#if defined(__sparc__)
+#ifndef ASI_PL
+#define ASI_PL 0x88
+#endif
+#endif
+
/* some important defines:
*
* WORDS_ALIGNED : if defined, the host cpu can only make word aligned
@@ -197,6 +203,10 @@
int val;
__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
return val;
+#elif defined(__sparc__)
+ uint16_t val;
+ __asm__ __volatile__ ("lduha [%1] %2, %0" : "=r" (val) : "r" (ptr), "i" (ASI_PL));
+ return val;
#else
uint8_t *p = ptr;
return p[0] | (p[1] << 8);
@@ -209,6 +219,10 @@
int val;
__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
return (int16_t)val;
+#elif defined(__sparc__)
+ int16_t val;
+ __asm__ __volatile__ ("lduha [%1] %2, %0" : "=r" (val) : "r" (ptr), "i" (ASI_PL));
+ return val;
#else
uint8_t *p = ptr;
return (int16_t)(p[0] | (p[1] << 8));
@@ -221,6 +235,10 @@
int val;
__asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
return val;
+#elif defined(__sparc__)
+ uint32_t val;
+ __asm__ __volatile__ ("lduwa [%1] %2, %0" : "=r" (val) : "r" (ptr), "i" (ASI_PL));
+ return val;
#else
uint8_t *p = ptr;
return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
@@ -240,6 +258,8 @@
{
#ifdef __powerpc__
__asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
+#elif defined(__sparc__)
+ __asm__ __volatile__ ("stha %0, [%1] %2" : : "r" (v), "r" (ptr), "i" (ASI_PL));
#else
uint8_t *p = ptr;
p[0] = v;
@@ -251,6 +271,8 @@
{
#ifdef __powerpc__
__asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
+#elif defined(__sparc__)
+ __asm__ __volatile__ ("stwa %0, [%1] %2" : : "r" (v), "r" (ptr), "i" (ASI_PL));
#else
uint8_t *p = ptr;
p[0] = v;