mirror of
https://github.com/colby-swandale/waterfoul
synced 2024-12-28 22:24:09 +01:00
53 lines
1.5 KiB
Ruby
53 lines
1.5 KiB
Ruby
require 'spec_helper'
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describe Waterfoul::Interrupt do
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before :each do
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$mmu = Waterfoul::MMU.new
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end
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subject { described_class }
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describe '.request_interupt' do
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context 'with INTERRUPT_VBLANK interrupt' do
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it 'sets bit for VBLANK interupt in IF register' do
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subject.request_interrupt Waterfoul::Interrupt::INTERRUPT_JOYPAD
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expect($mmu[0xFF0F]).to eq 0x10
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end
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end
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context 'with INTERRUPT_TIMER set' do
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it 'sets bit for timer interrupt in IF register' do
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subject.request_interrupt Waterfoul::Interrupt::INTERRUPT_TIMER
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expect($mmu[0xFF0F]).to eq 0x4
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end
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end
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end
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describe '.pending_interrupt' do
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context 'when bit 2 of IE and IF register is set' do
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before { $mmu[0xFF0F] = 0x4 }
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before { $mmu[0xFFFF] = 0x4 }
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it 'marks timer interrupt as pending' do
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expect(subject.pending_interrupt).to eq Waterfoul::Interrupt::INTERRUPT_TIMER
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end
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end
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context 'when bit 2 of IE register is 0' do
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before { $mmu[0xFF0F] = 0x4 }
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before { $mmu[0xFFFF] = 0x0 }
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it 'responds with no interrupts pending' do
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expect(subject.pending_interrupt).to eq Waterfoul::Interrupt::INTERRUPT_NONE
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end
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end
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context 'when 2 interrupts are pending' do
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before { $mmu[0xFF0F] = 0x3 }
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before { $mmu[0xFFFF] = 0xFF }
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it 'responds with higher priority interrupt' do
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expect(subject.pending_interrupt).to eq Waterfoul::Interrupt::INTERRUPT_VBLANK
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end
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end
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end
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end
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