22 commits

Author	SHA1	Message	Date
Colby Swandale	4896f791fa	fix incorrect behavior being tested on MBC1 read disabled memory	2016-09-26 23:03:50 +10:00
Colby Swandale	cb787edf43	simplify MBC ROM spec and make have reader for ROM ram	2016-09-26 23:03:01 +10:00
Colby Swandale	365724a3b5	redo logic spec to bring them up to date	2016-09-26 22:52:16 +10:00
Colby Swandale	1f78c4b27b	fixed cpu timing spec	2016-09-26 21:28:53 +10:00
Colby Swandale	4313b2dd63	cleaning up old code	2016-09-26 19:31:01 +10:00
Colby Swandale	2f5975b4f7	removed unused double for prefix specs	2016-09-26 17:31:40 +10:00
Colby Swandale	45d30cd4b2	updated misc specs to pass	2016-09-26 17:30:45 +10:00
Colby Swandale	5847a9a584	fixed specs for load instructions	2016-09-26 17:29:13 +10:00
Colby Swandale	a145bf8e9f	brain fart moment, the PC must always be increments on fetch instruction	2016-09-26 08:46:07 +10:00
Colby Swandale	e175b5bdf8	fixed breaking specs for jump instructions	2016-09-25 22:46:12 +10:00
Colby Swandale	c37d0d9b02	rename 'GPU' constants to 'PPU' in ppu specs	2016-09-25 19:08:17 +10:00
Colby Swandale	d62423d00a	cleanup and passing CPU specs	2016-09-25 19:06:55 +10:00
Colby Swandale	8b341762e4	fix PC being incorrectly incremented on interrupt and fixed relevent ... specs	2016-09-25 19:00:55 +10:00
Colby Swandale	d305150b05	passing some breaking specs	2016-09-18 23:02:01 +10:00
Colby	f962e68c73	add ppu spec, moved vblank into method and accessor mode + modeclock	2016-07-31 13:24:00 +10:00
Colby	c0780010a5	added serve interrupt spec	2016-07-23 20:58:36 +10:00
Colby	2bbfd679e2	rewote interrupt spec	2016-07-21 18:08:58 +10:00
Colby	e72058ec37	proper MBC1 implementation	2016-07-20 21:19:04 +10:00
Colby	b420384227	added specs for timer and mmu	2016-07-19 00:08:12 +10:00
Colby	7329ffa754	add DIV reset spec and DIV overflow reset spec	2016-07-18 21:08:20 +10:00
Colby	196235bce3	added timer	2016-07-17 22:05:51 +10:00
Colby	f6fcbba13e	init commit	2016-05-08 17:20:05 +10:00