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update timer to pass specs

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Colby 2016-07-19 00:08:46 +10:00
parent f5491fb543
commit a68e9339d8
1 changed files with 8 additions and 2 deletions
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10
lib/waterfoul/timer.rb
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@ -28,7 +28,13 @@ module Waterfoul
def inc_tima_register
tima = $mmu.read_byte 0xFF05
tima = (tima + 1) & 0xFF
if tima == 0xFF
tima = $mmu.read_byte 0xFF06
Interrupt.request_interrupt(Interrupt::INTERRUPT_TIMER)
else
tima = (tima + 1) & 0xFF
end
$mmu.write_byte 0xFF05, tima, hardware_operation: true
end
@ -46,7 +52,7 @@ module Waterfoul
end
def update
$mmu.read_byte 0xFF07
@register = $mmu.read_byte 0xFF07
end
def running?