diff --git a/lib/waterfoul/cpu.rb b/lib/waterfoul/cpu.rb
index 749f88e..d1fef75 100644
--- a/lib/waterfoul/cpu.rb
+++ b/lib/waterfoul/cpu.rb
@@ -74,30 +74,24 @@ module Waterfoul
     def step
       reset_tick
       serve_interrupt if @ime
-      instruction_byte = fetch_instruction
-      perform_instruction instruction_byte
+      check_halt if @halt
+      if halted?
+        @m = 4
+      else
+        instruction_byte = fetch_instruction
+        perform_instruction instruction_byte
+      end
       @timer.tick @m
     end
 
+    def check_halt
+      @halt = false if @pre_halt_interrupt != $mmu.read_byte(0xFF0F)
+    end
+
     def halted?
       @halt == true
     end
 
-    def halt_step
-      if @halt_cycles > 0
-        @halt_cycles -= 2
-        if @halt_cycles <= 0
-          @halt_cycles = 0
-          @halt = false
-        end
-      end
-
-      if @halt && Interrupt.pending_interupts != Interrupt::INTERRUPT_NONE && @halt_cycles == 0
-        @halt_cycles = HALT_CYCLES
-      end
-      @m = 2
-    end
-
     # Execute the instruction and 
     def perform_instruction(instruction)
       operation = OPCODE[instruction]
diff --git a/lib/waterfoul/instructions/misc.rb b/lib/waterfoul/instructions/misc.rb
index 8143d02..f211195 100644
--- a/lib/waterfoul/instructions/misc.rb
+++ b/lib/waterfoul/instructions/misc.rb
@@ -19,6 +19,7 @@ module Waterfoul
       # Halt CPU & LCD display until button pressed.
       # @flags - - - -
       def halt
+        @pre_halt_interrupt = $mmu.read_byte(0xFF0F)
         @halt = true
       end