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Merge pull request #6 from eregon/initialize-cpu-ivars

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Colby Swandale 2020-05-12 22:51:08 +10:00 committed by GitHub
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1 changed files with 4 additions and 3 deletions
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7
lib/waterfoul/cpu.rb
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@ -43,7 +43,7 @@ module Waterfoul
include Instructions::Prefix include Instructions::Prefix
# 8 bit registers # 8 bit registers
attr_reader :a, :b, :c, :d, :e, :f, :h, :l, :f attr_reader :a, :b, :c, :d, :e, :f, :h, :l
# CPU instruction cycle count # CPU instruction cycle count
attr_reader :m attr_reader :m
# 16 bit registers # 16 bit registers
@ -55,10 +55,11 @@ module Waterfoul
def initialize(options = {}) def initialize(options = {})
@pc = 0x0000 @pc = 0x0000
@sp = 0x0000 @sp = 0x0000
@a = @b = @c = @d = @e = @f = @h = @l = @f = 0x00 @a = @b = @c = @d = @e = @f = @h = @l = 0x00
@m = 0
@timer = Timer.new @timer = Timer.new
@ime = false @ime = false
@halt = false
reset_tick
end end
# This method emulates the CPU cycle process. Each instruction is # This method emulates the CPU cycle process. Each instruction is