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fixed cpu timing spec

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This commit is contained in:
Colby Swandale 2016-09-26 21:28:53 +10:00
parent 4313b2dd63
commit 1f78c4b27b
1 changed files with 25 additions and 36 deletions
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61
spec/cpu_timing_spec.rb
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@ -4,9 +4,9 @@ describe Waterfoul::CPU do
describe 'CPU instruction timings' do describe 'CPU instruction timings' do
before { $mmu = Waterfoul::MMU.new } before { $mmu = Waterfoul::MMU.new }
subject { Waterfoul::CPU.new }
ZERO_JUMP_INSTR = [:call_nz_a16, :call_nc_a16, :jp_nc_a16, :jp_nz_nn, before { subject.set_register :pc, 0x100 }
:ret_nc, :ret_nz, :jr_nc_r8, :jr_nz_r8, :jp_nz_a16].freeze before { subject.set_register :sp, 0x200 }
OPCODE_TIMINGS = [ OPCODE_TIMINGS = [
1, 3, 2, 2, 1, 1, 2, 1, 5, 2, 2, 2, 1, 1, 2, 1, 1, 3, 2, 2, 1, 1, 2, 1, 5, 2, 2, 2, 1, 1, 2, 1,
@ -46,41 +46,30 @@ describe Waterfoul::CPU do
3, 3, 2, 1, 0, 4, 2, 4, 3, 2, 4, 1, 0, 0, 2, 4, 3, 3, 2, 1, 0, 4, 2, 4, 3, 2, 4, 1, 0, 0, 2, 4,
].freeze ].freeze
Waterfoul::CPU::OPCODE.each_with_index do |instruction, index| ZERO_JUMP_INSTR = [:call_nz_a16, :call_nc_a16, :jp_nc_a16, :jp_nz_nn,
next if instruction == :prefix_cb :ret_nc, :ret_nz, :jr_nc_r8, :jr_nz_r8, :jp_nz_a16].freeze
describe "\##{instruction}" do
context "when flags reset" do describe 'instruction timings' do
if ZERO_JUMP_INSTR.include? instruction Waterfoul::CPU::OPCODE.each_with_index do |instruction, index|
cpu = Waterfoul::CPU.new pc: 0xABAC, sp: 0xFFF0, f: 0xF0 next if instruction == :prefix_cb || instruction == :xx
else
cpu = Waterfoul::CPU.new pc: 0xABAC, sp: 0xFFF0, f: 0x00 describe instruction do
context 'with all status flag bits reset' do
before { subject.set_register :f, 0xF0 } if ZERO_JUMP_INSTR.include?(instruction)
it 'sets the correct instruction timing' do
instruction_cycles = OPCODE_TIMINGS[index]
subject.perform_instruction index
expect(subject.m).to eq (instruction_cycles * 4)
end
end end
# skip the test if the instruction is not implemnted context 'with all status flag bits set' do
next if instruction == :xx || instruction == :prefix_cb before { subject.set_register :f, 0xF0 } unless ZERO_JUMP_INSTR.include?(instruction)
it 'sets the correct instruction timing' do
before { allow(cpu).to receive(:fetch_instruction).and_return(index) } instruction_cycles = OPCODE_CONDITIONAL_TIMINGS[index]
it "sets clock cycle" do subject.perform_instruction index
instruction_cycles = OPCODE_TIMINGS[index] expect(subject.m).to eq (instruction_cycles * 4)
cpu.perform_instruction index end
expect(cpu.m).to eq instruction_cycles
end
end
context 'with all flags set' do
if ZERO_JUMP_INSTR.include? instruction
cpu = Waterfoul::CPU.new pc: 0xABAC, sp: 0xFFF0, f: 0x00
else
cpu = Waterfoul::CPU.new pc: 0xABAC, sp: 0xFFF0, f: 0xF0
end
next if instruction == :xx || instruction == :prefix_cb
before { allow(cpu).to receive(:fetch_instruction).and_return(index) }
it 'sets clock cycle' do
instruction_cycles = OPCODE_CONDITIONAL_TIMINGS[index]
cpu.perform_instruction index
expect(cpu.m).to eq instruction_cycles
end end
end end
end end