slackbuilds_ponce/academic/verilog
dsomero d0c108251a various: Update find command to match template.
Signed-off-by: dsomero <xgizzmo@slackbuilds.org>
2013-11-22 02:37:19 -05:00
..
README academic/verilog: Added to 13.0 repository 2010-05-13 00:57:23 +02:00
slack-desc various: Fix slack-desc formatting and comment nit picks. 2013-11-22 02:29:22 -05:00
verilog.info academic/verilog: Updated for version 0.9.7. 2013-11-05 20:14:24 -06:00
verilog.SlackBuild various: Update find command to match template. 2013-11-22 02:37:19 -05:00

Icarus Verilog is a Verilog simulation and synthesis tool.  It operates as
a compiler, compiling source code written in Verilog (IEEE-1364) into some 
target format.  For batch simulation, the compiler can generate an intermediate
form called vvp assembly.  This intermediate form is executed by the 'vvp' 
command.  For synthesis, the compiler generates netlists in the desired format.