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fd672e3c99
Signed-off-by: Matteo Bernardini <ponce@slackbuilds.org>
5 lines
209 B
Text
5 lines
209 B
Text
Open-source interpreted Verilog simulator with a feature set and
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performance similar to Verilog-XL.
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Implements all IEEE 1364-1995 features along with some Verilog-2001
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features.
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Full support for Verilog PLIs.
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