slackbuilds_ponce/academic/verilog
Dave Woodfall b66b94d5ec academic/verilog: Updated for version 11.0.
Signed-off-by: Dave Woodfall <dave@slackbuilds.org>
2022-03-03 10:24:49 +00:00
..
README
slack-desc
verilog.info academic/verilog: Updated for version 11.0. 2022-03-03 10:24:49 +00:00
verilog.SlackBuild academic/verilog: Updated for version 11.0. 2022-03-03 10:24:49 +00:00

Icarus Verilog is a Verilog simulation and synthesis tool.  It operates
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format.  For batch simulation, the compiler can
generate an intermediate form called vvp assembly.  This intermediate
form is executed by the 'vvp' command.  For synthesis, the compiler
generates netlists in the desired format.