mirror of
https://github.com/Ponce/slackbuilds
synced 2024-11-22 19:44:21 +01:00
9a5f389f29
Signed-off-by: B. Watson <yalhcru@gmail.com> Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
6 lines
385 B
Text
6 lines
385 B
Text
Icarus Verilog is a Verilog simulation and synthesis tool. It operates
|
|
as a compiler, compiling source code written in Verilog (IEEE-1364)
|
|
into some target format. For batch simulation, the compiler can
|
|
generate an intermediate form called vvp assembly. This intermediate
|
|
form is executed by the 'vvp' command. For synthesis, the compiler
|
|
generates netlists in the desired format.
|