slackbuilds_ponce/academic/verilog
Willy Sudiarto Raharjo 48fbd653f5
academic/verilog: Fix download url.
Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
2022-11-05 12:56:05 +07:00
..
README
slack-desc
verilog.info
verilog.SlackBuild

Icarus Verilog is a Verilog simulation and synthesis tool.  It operates
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format.  For batch simulation, the compiler can
generate an intermediate form called vvp assembly.  This intermediate
form is executed by the 'vvp' command.  For synthesis, the compiler
generates netlists in the desired format.