slackbuilds_ponce/academic/DRAMsim3
Andrew Clemons 95f73609d5
academic/DRAMsim3: Fix github tarball handling.
Signed-off-by: Andrew Clemons <andrew.clemons@gmail.com>

Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
2022-11-05 21:15:16 +07:00
..
DRAMsim3.info
DRAMsim3.SlackBuild
README
slack-desc

  DRAMsim3 models the timing paramaters and memory controller behavior
for several DRAM protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5,
GDDR6, HBM, HMC, STT-MRAM. It is implemented in C++ as an objected
oriented model that includes a parameterized DRAM bank model, DRAM
controllers, command queues and system-level interfaces to interact
with a CPU simulator (GEM5, ZSim) or trace workloads. It is designed
to be accurate, portable and parallel.