slackbuilds_ponce/academic/verilog
Erik Hanson 4248415dde Add REQUIRED field to .info files.
Signed-off-by: Erik Hanson <erik@slackbuilds.org>
2012-08-19 21:57:51 -05:00
..
README academic/verilog: Added to 13.0 repository 2010-05-13 00:57:23 +02:00
slack-desc academic/verilog: Added to 13.0 repository 2010-05-13 00:57:23 +02:00
verilog.info Add REQUIRED field to .info files. 2012-08-19 21:57:51 -05:00
verilog.SlackBuild academic/verilog: Updated for version 0.9.4. 2011-03-24 19:23:15 -05:00

Icarus Verilog is a Verilog simulation and synthesis tool.  It operates as
a compiler, compiling source code written in Verilog (IEEE-1364) into some 
target format.  For batch simulation, the compiler can generate an intermediate
form called vvp assembly.  This intermediate form is executed by the 'vvp' 
command.  For synthesis, the compiler generates netlists in the desired format.