slackbuilds_ponce/academic/verilator/verilator.info
Charles Daniels ab05ac3f2e
academic/verilator: Added (Verilog HDL Simulator).
Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
2020-03-20 19:30:05 +07:00

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PRGNAM="verilator"
VERSION="4.030"
HOMEPAGE="https://www.veripool.org/wiki/verilator"
DOWNLOAD="https://www.veripool.org/ftp/verilator-4.030.tgz"
MD5SUM="f412f817a8eeb142f6d27684e5fd4809"
DOWNLOAD_x86_64=""
MD5SUM_x86_64=""
REQUIRES="python3"
MAINTAINER="Charles Daniels"
EMAIL="charles [at] cdaniels [dot] net"