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70 lines
2.6 KiB
Diff
70 lines
2.6 KiB
Diff
From 02d0027a89dc49875a41e939498936874a32360f Mon Sep 17 00:00:00 2001
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From: Andrew Cooper <andrew.cooper3@citrix.com>
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Date: Fri, 13 Apr 2018 15:42:34 +0000
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Subject: [PATCH] x86/msr: Virtualise MSR_SPEC_CTRL.SSBD for guests to use
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Almost all infrastructure is already in place. Update the reserved bits
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calculation in guest_wrmsr(), and offer SSBD to guests by default.
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Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Reviewed-by: Jan Beulich <jbeulich@suse.com>
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---
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xen/arch/x86/msr.c | 8 ++++++--
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xen/include/public/arch-x86/cpufeatureset.h | 2 +-
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2 files changed, 7 insertions(+), 3 deletions(-)
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diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
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index 48d061d..21219c4 100644
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--- a/xen/arch/x86/msr.c
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+++ b/xen/arch/x86/msr.c
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@@ -178,6 +178,8 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
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switch ( msr )
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{
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+ uint64_t rsvd;
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+
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case MSR_INTEL_PLATFORM_INFO:
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case MSR_ARCH_CAPABILITIES:
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/* Read-only */
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@@ -213,8 +215,10 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
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* Note: SPEC_CTRL_STIBP is specified as safe to use (i.e. ignored)
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* when STIBP isn't enumerated in hardware.
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*/
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+ rsvd = ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
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+ (cp->feat.ssbd ? SPEC_CTRL_SSBD : 0));
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- if ( val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
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+ if ( val & rsvd )
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goto gp_fault; /* Rsvd bit set? */
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vp->spec_ctrl.raw = val;
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@@ -233,12 +237,12 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
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case MSR_INTEL_MISC_FEATURES_ENABLES:
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{
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- uint64_t rsvd = ~0ull;
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bool old_cpuid_faulting = vp->misc_features_enables.cpuid_faulting;
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if ( !vp->misc_features_enables.available )
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goto gp_fault;
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+ rsvd = ~0ull;
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if ( dp->plaform_info.cpuid_faulting )
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rsvd &= ~MSR_MISC_FEATURES_CPUID_FAULTING;
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diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
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index 7acf822..c721c12 100644
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--- a/xen/include/public/arch-x86/cpufeatureset.h
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+++ b/xen/include/public/arch-x86/cpufeatureset.h
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@@ -245,7 +245,7 @@ XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single
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XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */
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XEN_CPUFEATURE(STIBP, 9*32+27) /*A! STIBP */
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XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /* IA32_ARCH_CAPABILITIES MSR */
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-XEN_CPUFEATURE(SSBD, 9*32+31) /* MSR_SPEC_CTRL.SSBD available */
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+XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */
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#endif /* XEN_CPUFEATURE */
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--
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2.1.4
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