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123 lines
4.3 KiB
Diff
123 lines
4.3 KiB
Diff
From 918320daf34931cd5c1c0d9c439ce853f6575970 Mon Sep 17 00:00:00 2001
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From: Andrew Cooper <andrew.cooper3@citrix.com>
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Date: Thu, 26 Apr 2018 10:56:28 +0100
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Subject: [PATCH] x86/AMD: Mitigations for GPZ SP4 - Speculative Store Bypass
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AMD processors will execute loads and stores with the same base register in
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program order, which is typically how a compiler emits code.
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Therefore, by default no mitigating actions are taken, despite there being
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corner cases which are vulnerable to the issue.
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For performance testing, or for users with particularly sensitive workloads,
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the `spec-ctrl=ssbd` command line option is available to force Xen to disable
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Memory Disambiguation on applicable hardware.
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Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Reviewed-by: Jan Beulich <jbeulich@suse.com>
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---
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docs/misc/xen-command-line.markdown | 7 ++++++-
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xen/arch/x86/cpu/amd.c | 20 ++++++++++++++++++++
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xen/arch/x86/spec_ctrl.c | 3 +++
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xen/include/asm-x86/spec_ctrl.h | 1 +
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4 files changed, 30 insertions(+), 1 deletion(-)
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diff --git a/docs/misc/xen-command-line.markdown b/docs/misc/xen-command-line.markdown
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index 43a6ddb..4e0e580 100644
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--- a/docs/misc/xen-command-line.markdown
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+++ b/docs/misc/xen-command-line.markdown
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@@ -1703,7 +1703,7 @@ false disable the quirk workaround, which is also the default.
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### spec-ctrl (x86)
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> `= List of [ <bool>, xen=<bool>, {pv,hvm,msr-sc,rsb}=<bool>,
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-> bti-thunk=retpoline|lfence|jmp, {ibrs,ibpb}=<bool> ]`
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+> bti-thunk=retpoline|lfence|jmp, {ibrs,ibpb,ssbd}=<bool> ]`
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Controls for speculative execution sidechannel mitigations. By default, Xen
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will pick the most appropriate mitigations based on compiled in support,
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@@ -1747,6 +1747,11 @@ On hardware supporting IBPB (Indirect Branch Prediction Barrier), the `ibpb=`
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option can be used to force (the default) or prevent Xen from issuing branch
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prediction barriers on vcpu context switches.
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+On hardware supporting SSBD (Speculative Store Bypass Disable), the `ssbd=`
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+option can be used to force or prevent Xen using the feature itself. On AMD
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+hardware, this is a global option applied at boot, and not virtualised for
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+guest use.
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+
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### sync\_console
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> `= <boolean>`
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diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
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index fc9677f..458a3fe 100644
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--- a/xen/arch/x86/cpu/amd.c
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+++ b/xen/arch/x86/cpu/amd.c
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@@ -9,6 +9,7 @@
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#include <asm/amd.h>
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#include <asm/hvm/support.h>
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#include <asm/setup.h> /* amd_init_cpu */
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+#include <asm/spec_ctrl.h>
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#include <asm/acpi.h>
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#include <asm/apic.h>
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@@ -594,6 +595,25 @@ static void init_amd(struct cpuinfo_x86 *c)
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c->x86_capability);
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}
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+ /*
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+ * If the user has explicitly chosen to disable Memory Disambiguation
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+ * to mitigiate Speculative Store Bypass, poke the appropriate MSR.
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+ */
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+ if (opt_ssbd) {
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+ int bit = -1;
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+
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+ switch (c->x86) {
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+ case 0x15: bit = 54; break;
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+ case 0x16: bit = 33; break;
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+ case 0x17: bit = 10; break;
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+ }
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+
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+ if (bit >= 0 && !rdmsr_safe(MSR_AMD64_LS_CFG, value)) {
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+ value |= 1ull << bit;
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+ wrmsr_safe(MSR_AMD64_LS_CFG, value);
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+ }
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+ }
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+
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/* MFENCE stops RDTSC speculation */
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if (!cpu_has_lfence_dispatch)
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__set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
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diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
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index 4f9282f..e326056 100644
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--- a/xen/arch/x86/spec_ctrl.c
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+++ b/xen/arch/x86/spec_ctrl.c
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@@ -43,6 +43,7 @@ static enum ind_thunk {
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} opt_thunk __initdata = THUNK_DEFAULT;
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static int8_t __initdata opt_ibrs = -1;
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bool __read_mostly opt_ibpb = true;
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+bool __read_mostly opt_ssbd = false;
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bool __initdata bsp_delay_spec_ctrl;
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uint8_t __read_mostly default_xen_spec_ctrl;
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@@ -164,6 +165,8 @@ static int __init parse_spec_ctrl(const char *s)
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opt_ibrs = val;
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else if ( (val = parse_boolean("ibpb", s, ss)) >= 0 )
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opt_ibpb = val;
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+ else if ( (val = parse_boolean("ssbd", s, ss)) >= 0 )
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+ opt_ssbd = val;
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else
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rc = -EINVAL;
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diff --git a/xen/include/asm-x86/spec_ctrl.h b/xen/include/asm-x86/spec_ctrl.h
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index c6a38f4..4678a40 100644
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--- a/xen/include/asm-x86/spec_ctrl.h
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+++ b/xen/include/asm-x86/spec_ctrl.h
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@@ -27,6 +27,7 @@
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void init_speculation_mitigations(void);
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extern bool opt_ibpb;
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+extern bool opt_ssbd;
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extern bool bsp_delay_spec_ctrl;
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extern uint8_t default_xen_spec_ctrl;
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--
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2.1.4
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