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132 lines
5.1 KiB
Diff
132 lines
5.1 KiB
Diff
From bce7a2145abc3c7e5bfd7e2168714d194124a3ab Mon Sep 17 00:00:00 2001
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From: Andrew Cooper <andrew.cooper3@citrix.com>
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Date: Tue, 1 May 2018 11:59:03 +0100
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Subject: [PATCH] x86/cpuid: Improvements to guest policies for speculative
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sidechannel features
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If Xen isn't virtualising MSR_SPEC_CTRL for guests, IBRSB shouldn't be
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advertised. It is not currently possible to express this via the existing
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command line options, but such an ability will be introduced.
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Another useful option in some usecases is to offer IBPB without IBRS. When a
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guest kernel is known to be compatible (uses retpoline and knows about the AMD
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IBPB feature bit), an administrator with pre-Skylake hardware may wish to hide
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IBRS. This allows the VM to have full protection, without Xen or the VM
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needing to touch MSR_SPEC_CTRL, which can reduce the overhead of Spectre
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mitigations.
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Break the logic common to both PV and HVM CPUID calculations into a common
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helper, to avoid duplication.
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Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Reviewed-by: Wei Liu <wei.liu2@citrix.com>
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Reviewed-by: Jan Beulich <jbeulich@suse.com>
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Release-acked-by: Juergen Gross <jgross@suse.com>
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(cherry picked from commit cb06b308ec71b23f37a44f5e2351fe2cae0306e9)
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---
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xen/arch/x86/cpuid.c | 60 ++++++++++++++++++++++++++++++++--------------------
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1 file changed, 37 insertions(+), 23 deletions(-)
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diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
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index b3c9ac6..b45b145 100644
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--- a/xen/arch/x86/cpuid.c
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+++ b/xen/arch/x86/cpuid.c
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@@ -368,6 +368,28 @@ static void __init calculate_host_policy(void)
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}
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}
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+static void __init guest_common_feature_adjustments(uint32_t *fs)
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+{
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+ /* Unconditionally claim to be able to set the hypervisor bit. */
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+ __set_bit(X86_FEATURE_HYPERVISOR, fs);
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+
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+ /*
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+ * If IBRS is offered to the guest, unconditionally offer STIBP. It is a
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+ * nop on non-HT hardware, and has this behaviour to make heterogeneous
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+ * setups easier to manage.
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+ */
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+ if ( test_bit(X86_FEATURE_IBRSB, fs) )
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+ __set_bit(X86_FEATURE_STIBP, fs);
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+
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+ /*
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+ * On hardware which supports IBRS/IBPB, we can offer IBPB independently
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+ * of IBRS by using the AMD feature bit. An administrator may wish for
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+ * performance reasons to offer IBPB without IBRS.
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+ */
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+ if ( host_cpuid_policy.feat.ibrsb )
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+ __set_bit(X86_FEATURE_IBPB, fs);
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+}
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+
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static void __init calculate_pv_max_policy(void)
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{
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struct cpuid_policy *p = &pv_max_cpuid_policy;
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@@ -380,18 +402,14 @@ static void __init calculate_pv_max_policy(void)
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for ( i = 0; i < ARRAY_SIZE(pv_featureset); ++i )
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pv_featureset[i] &= pv_featuremask[i];
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- /* Unconditionally claim to be able to set the hypervisor bit. */
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- __set_bit(X86_FEATURE_HYPERVISOR, pv_featureset);
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-
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- /* On hardware with IBRS/IBPB support, there are further adjustments. */
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- if ( test_bit(X86_FEATURE_IBRSB, pv_featureset) )
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- {
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- /* Offer STIBP unconditionally. It is a nop on non-HT hardware. */
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- __set_bit(X86_FEATURE_STIBP, pv_featureset);
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+ /*
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+ * If Xen isn't virtualising MSR_SPEC_CTRL for PV guests because of
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+ * administrator choice, hide the feature.
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+ */
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+ if ( !boot_cpu_has(X86_FEATURE_SC_MSR_PV) )
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+ __clear_bit(X86_FEATURE_IBRSB, pv_featureset);
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- /* AMD's IBPB is a subset of IBRS/IBPB. */
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- __set_bit(X86_FEATURE_IBPB, pv_featureset);
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- }
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+ guest_common_feature_adjustments(pv_featureset);
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sanitise_featureset(pv_featureset);
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cpuid_featureset_to_policy(pv_featureset, p);
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@@ -419,9 +437,6 @@ static void __init calculate_hvm_max_policy(void)
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for ( i = 0; i < ARRAY_SIZE(hvm_featureset); ++i )
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hvm_featureset[i] &= hvm_featuremask[i];
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- /* Unconditionally claim to be able to set the hypervisor bit. */
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- __set_bit(X86_FEATURE_HYPERVISOR, hvm_featureset);
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-
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/*
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* Xen can provide an APIC emulation to HVM guests even if the host's APIC
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* isn't enabled.
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@@ -438,6 +453,13 @@ static void __init calculate_hvm_max_policy(void)
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__set_bit(X86_FEATURE_SEP, hvm_featureset);
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/*
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+ * If Xen isn't virtualising MSR_SPEC_CTRL for HVM guests because of
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+ * administrator choice, hide the feature.
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+ */
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+ if ( !boot_cpu_has(X86_FEATURE_SC_MSR_HVM) )
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+ __clear_bit(X86_FEATURE_IBRSB, hvm_featureset);
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+
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+ /*
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* With VT-x, some features are only supported by Xen if dedicated
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* hardware support is also available.
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*/
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@@ -450,15 +472,7 @@ static void __init calculate_hvm_max_policy(void)
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__clear_bit(X86_FEATURE_XSAVES, hvm_featureset);
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}
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- /* On hardware with IBRS/IBPB support, there are further adjustments. */
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- if ( test_bit(X86_FEATURE_IBRSB, hvm_featureset) )
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- {
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- /* Offer STIBP unconditionally. It is a nop on non-HT hardware. */
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- __set_bit(X86_FEATURE_STIBP, hvm_featureset);
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-
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- /* AMD's IBPB is a subset of IBRS/IBPB. */
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- __set_bit(X86_FEATURE_IBPB, hvm_featureset);
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- }
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+ guest_common_feature_adjustments(hvm_featureset);
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sanitise_featureset(hvm_featureset);
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cpuid_featureset_to_policy(hvm_featureset, p);
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--
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2.1.4
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