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https://github.com/Ponce/slackbuilds
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138 lines
5 KiB
Diff
138 lines
5 KiB
Diff
From d7b345e4ca136a995bfaaf2ee20901ee20e63570 Mon Sep 17 00:00:00 2001
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From: Andrew Cooper <andrew.cooper3@citrix.com>
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Date: Tue, 17 Apr 2018 14:15:04 +0100
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Subject: [PATCH] x86/spec_ctrl: Express Xen's choice of MSR_SPEC_CTRL value as
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a variable
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At the moment, we have two different encodings of Xen's MSR_SPEC_CTRL value,
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which is a side effect of how the Spectre series developed. One encoding is
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via an alias with the bottom bit of bti_ist_info, and can encode IBRS or not,
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but not other configurations such as STIBP.
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Break Xen's value out into a separate variable (in the top of stack block for
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XPTI reasons) and use this instead of bti_ist_info in the IST path.
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Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Reviewed-by: Wei Liu <wei.liu2@citrix.com>
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Reviewed-by: Jan Beulich <jbeulich@suse.com>
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Release-acked-by: Juergen Gross <jgross@suse.com>
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(cherry picked from commit 66dfae0f32bfbc899c2f3446d5ee57068cb7f957)
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---
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xen/arch/x86/spec_ctrl.c | 8 +++++---
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xen/arch/x86/x86_64/asm-offsets.c | 1 +
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xen/include/asm-x86/current.h | 1 +
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xen/include/asm-x86/spec_ctrl.h | 2 ++
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xen/include/asm-x86/spec_ctrl_asm.h | 8 ++------
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5 files changed, 11 insertions(+), 9 deletions(-)
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diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
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index dc90743..1143521 100644
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--- a/xen/arch/x86/spec_ctrl.c
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+++ b/xen/arch/x86/spec_ctrl.c
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@@ -38,6 +38,7 @@ static int8_t __initdata opt_ibrs = -1;
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static bool __initdata opt_rsb_native = true;
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static bool __initdata opt_rsb_vmexit = true;
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bool __read_mostly opt_ibpb = true;
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+uint8_t __read_mostly default_xen_spec_ctrl;
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uint8_t __read_mostly default_bti_ist_info;
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static int __init parse_bti(const char *s)
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@@ -285,11 +286,14 @@ void __init init_speculation_mitigations(void)
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* guests.
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*/
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if ( ibrs )
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+ {
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+ default_xen_spec_ctrl |= SPEC_CTRL_IBRS;
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setup_force_cpu_cap(X86_FEATURE_XEN_IBRS_SET);
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+ }
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else
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setup_force_cpu_cap(X86_FEATURE_XEN_IBRS_CLEAR);
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- default_bti_ist_info |= BTI_IST_WRMSR | ibrs;
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+ default_bti_ist_info |= BTI_IST_WRMSR;
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}
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/*
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@@ -330,8 +334,6 @@ void __init init_speculation_mitigations(void)
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static void __init __maybe_unused build_assertions(void)
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{
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- /* The optimised assembly relies on this alias. */
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- BUILD_BUG_ON(BTI_IST_IBRS != SPEC_CTRL_IBRS);
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}
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/*
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diff --git a/xen/arch/x86/x86_64/asm-offsets.c b/xen/arch/x86/x86_64/asm-offsets.c
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index 13478d4..0726147 100644
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--- a/xen/arch/x86/x86_64/asm-offsets.c
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+++ b/xen/arch/x86/x86_64/asm-offsets.c
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@@ -142,6 +142,7 @@ void __dummy__(void)
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OFFSET(CPUINFO_xen_cr3, struct cpu_info, xen_cr3);
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OFFSET(CPUINFO_pv_cr3, struct cpu_info, pv_cr3);
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OFFSET(CPUINFO_shadow_spec_ctrl, struct cpu_info, shadow_spec_ctrl);
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+ OFFSET(CPUINFO_xen_spec_ctrl, struct cpu_info, xen_spec_ctrl);
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OFFSET(CPUINFO_use_shadow_spec_ctrl, struct cpu_info, use_shadow_spec_ctrl);
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OFFSET(CPUINFO_bti_ist_info, struct cpu_info, bti_ist_info);
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DEFINE(CPUINFO_sizeof, sizeof(struct cpu_info));
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diff --git a/xen/include/asm-x86/current.h b/xen/include/asm-x86/current.h
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index 4678a0f..d10b13c 100644
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--- a/xen/include/asm-x86/current.h
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+++ b/xen/include/asm-x86/current.h
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@@ -56,6 +56,7 @@ struct cpu_info {
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/* See asm-x86/spec_ctrl_asm.h for usage. */
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unsigned int shadow_spec_ctrl;
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+ uint8_t xen_spec_ctrl;
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bool use_shadow_spec_ctrl;
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uint8_t bti_ist_info;
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diff --git a/xen/include/asm-x86/spec_ctrl.h b/xen/include/asm-x86/spec_ctrl.h
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index 5ab4ff3..5e4fc84 100644
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--- a/xen/include/asm-x86/spec_ctrl.h
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+++ b/xen/include/asm-x86/spec_ctrl.h
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@@ -27,6 +27,7 @@
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void init_speculation_mitigations(void);
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extern bool opt_ibpb;
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+extern uint8_t default_xen_spec_ctrl;
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extern uint8_t default_bti_ist_info;
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static inline void init_shadow_spec_ctrl_state(void)
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@@ -34,6 +35,7 @@ static inline void init_shadow_spec_ctrl_state(void)
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struct cpu_info *info = get_cpu_info();
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info->shadow_spec_ctrl = info->use_shadow_spec_ctrl = 0;
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+ info->xen_spec_ctrl = default_xen_spec_ctrl;
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info->bti_ist_info = default_bti_ist_info;
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}
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diff --git a/xen/include/asm-x86/spec_ctrl_asm.h b/xen/include/asm-x86/spec_ctrl_asm.h
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index 1f2b6f3..697da13 100644
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--- a/xen/include/asm-x86/spec_ctrl_asm.h
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+++ b/xen/include/asm-x86/spec_ctrl_asm.h
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@@ -21,7 +21,6 @@
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#define __X86_SPEC_CTRL_ASM_H__
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/* Encoding of the bottom bits in cpuinfo.bti_ist_info */
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-#define BTI_IST_IBRS (1 << 0)
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#define BTI_IST_WRMSR (1 << 1)
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#define BTI_IST_RSB (1 << 2)
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@@ -286,12 +285,9 @@
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setz %dl
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and %dl, STACK_CPUINFO_FIELD(use_shadow_spec_ctrl)(%r14)
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- /*
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- * Load Xen's intended value. SPEC_CTRL_IBRS vs 0 is encoded in the
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- * bottom bit of bti_ist_info, via a deliberate alias with BTI_IST_IBRS.
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- */
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+ /* Load Xen's intended value. */
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mov $MSR_SPEC_CTRL, %ecx
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- and $BTI_IST_IBRS, %eax
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+ movzbl STACK_CPUINFO_FIELD(xen_spec_ctrl)(%r14), %eax
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xor %edx, %edx
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wrmsr
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--
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2.1.4
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