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110 lines
3.8 KiB
Diff
110 lines
3.8 KiB
Diff
From 13fafdf5c97d3bc2a8851c4d1796feac0f82d498 Mon Sep 17 00:00:00 2001
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From: Andrew Cooper <andrew.cooper3@citrix.com>
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Date: Thu, 26 Apr 2018 12:21:00 +0100
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Subject: [PATCH] x86/spec_ctrl: Read MSR_ARCH_CAPABILITIES only once
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Make it available from the beginning of init_speculation_mitigations(), and
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pass it into appropriate functions. Fix an RSBA typo while moving the
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affected comment.
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Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Reviewed-by: Wei Liu <wei.liu2@citrix.com>
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Reviewed-by: Jan Beulich <jbeulich@suse.com>
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Release-acked-by: Juergen Gross <jgross@suse.com>
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(cherry picked from commit d6c65187252a6c1810fd24c4d46f812840de8d3c)
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---
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xen/arch/x86/spec_ctrl.c | 34 ++++++++++++++--------------------
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1 file changed, 14 insertions(+), 20 deletions(-)
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diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
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index fa67a0f..dc90743 100644
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--- a/xen/arch/x86/spec_ctrl.c
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+++ b/xen/arch/x86/spec_ctrl.c
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@@ -81,18 +81,15 @@ static int __init parse_bti(const char *s)
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}
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custom_param("bti", parse_bti);
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-static void __init print_details(enum ind_thunk thunk)
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+static void __init print_details(enum ind_thunk thunk, uint64_t caps)
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{
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unsigned int _7d0 = 0, e8b = 0, tmp;
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- uint64_t caps = 0;
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/* Collect diagnostics about available mitigations. */
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if ( boot_cpu_data.cpuid_level >= 7 )
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cpuid_count(7, 0, &tmp, &tmp, &tmp, &_7d0);
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if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 )
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cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp);
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- if ( _7d0 & cpufeat_mask(X86_FEATURE_ARCH_CAPS) )
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- rdmsrl(MSR_ARCH_CAPABILITIES, caps);
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printk(XENLOG_DEBUG "Speculative mitigation facilities:\n");
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@@ -125,7 +122,7 @@ static void __init print_details(enum ind_thunk thunk)
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}
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/* Calculate whether Retpoline is known-safe on this CPU. */
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-static bool __init retpoline_safe(void)
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+static bool __init retpoline_safe(uint64_t caps)
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{
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unsigned int ucode_rev = this_cpu(ucode_cpu_info).cpu_sig.rev;
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@@ -136,19 +133,12 @@ static bool __init retpoline_safe(void)
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boot_cpu_data.x86 != 6 )
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return false;
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- if ( boot_cpu_has(X86_FEATURE_ARCH_CAPS) )
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- {
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- uint64_t caps;
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-
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- rdmsrl(MSR_ARCH_CAPABILITIES, caps);
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-
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- /*
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- * RBSA may be set by a hypervisor to indicate that we may move to a
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- * processor which isn't retpoline-safe.
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- */
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- if ( caps & ARCH_CAPS_RSBA )
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- return false;
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- }
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+ /*
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+ * RSBA may be set by a hypervisor to indicate that we may move to a
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+ * processor which isn't retpoline-safe.
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+ */
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+ if ( caps & ARCH_CAPS_RSBA )
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+ return false;
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switch ( boot_cpu_data.x86_model )
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{
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@@ -218,6 +208,10 @@ void __init init_speculation_mitigations(void)
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{
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enum ind_thunk thunk = THUNK_DEFAULT;
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bool ibrs = false;
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+ uint64_t caps = 0;
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+
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+ if ( boot_cpu_has(X86_FEATURE_ARCH_CAPS) )
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+ rdmsrl(MSR_ARCH_CAPABILITIES, caps);
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/*
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* Has the user specified any custom BTI mitigations? If so, follow their
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@@ -246,7 +240,7 @@ void __init init_speculation_mitigations(void)
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* On Intel hardware, we'd like to use retpoline in preference to
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* IBRS, but only if it is safe on this hardware.
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*/
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- else if ( retpoline_safe() )
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+ else if ( retpoline_safe(caps) )
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thunk = THUNK_RETPOLINE;
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else if ( boot_cpu_has(X86_FEATURE_IBRSB) )
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ibrs = true;
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@@ -331,7 +325,7 @@ void __init init_speculation_mitigations(void)
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/* (Re)init BSP state now that default_bti_ist_info has been calculated. */
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init_shadow_spec_ctrl_state();
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- print_details(thunk);
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+ print_details(thunk, caps);
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}
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static void __init __maybe_unused build_assertions(void)
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--
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2.1.4
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