mirror of
https://github.com/Ponce/slackbuilds
synced 2024-11-06 08:26:50 +01:00
19 lines
1 KiB
Text
19 lines
1 KiB
Text
# HOW TO EDIT THIS FILE:
|
||
# The "handy ruler" below makes it easier to edit a package description.
|
||
# Line up the first '|' above the ':' following the base package name, and
|
||
# the '|' on the right side marks the last column you can put a character in.
|
||
# You must make exactly 11 lines for the formatting to be correct. It's also
|
||
# customary to leave one space after the ':' except on otherwise blank lines.
|
||
|
||
|-----handy-ruler------------------------------------------------------|
|
||
verilator: verilator (the fastest free Verilog HDL simulator)
|
||
verilator:
|
||
verilator: Verilator is invoked with parameters similar to GCC or Synopsys’s VCS.
|
||
verilator: It "Verilates" the specified synthesizable Verilog or SystemVerilog
|
||
verilator: code by reading it, performing lint checks, and optionally inserting
|
||
verilator: assertion checks and coverage-analysis points. It outputs single- or
|
||
verilator: multi-threaded .cpp and .h files, the "Verilated" code.
|
||
verilator:
|
||
verilator: homepage: https://www.veripool.org/wiki/verilator
|
||
verilator:
|
||
verilator:
|