slackbuilds_ponce/academic/verilog
Willy Sudiarto Raharjo 6731e7a316 academic/verilog: Updated for version 0.9.7.
Signed-off-by: Willy Sudiarto Raharjo <willysr@slackware-id.org>
Signed-off-by: Robby Workman <rworkman@slackbuilds.org>
2013-11-05 20:14:24 -06:00
..
README
slack-desc
verilog.info
verilog.SlackBuild

Icarus Verilog is a Verilog simulation and synthesis tool.  It operates as
a compiler, compiling source code written in Verilog (IEEE-1364) into some 
target format.  For batch simulation, the compiler can generate an intermediate
form called vvp assembly.  This intermediate form is executed by the 'vvp' 
command.  For synthesis, the compiler generates netlists in the desired format.