slackbuilds_ponce/development/yosys/yosys.info
William PC 66f5af0cd3
development/yosys: Added (A framework for Verilog RTL synthesis)
Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
2022-11-05 21:15:11 +07:00

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PRGNAM="yosys"
VERSION="0.22"
HOMEPAGE="https://yosyshq.net/yosys"
DOWNLOAD="https://github.com/YosysHQ/yosys/archive/refs/tags/yosys-0.22.tar.gz"
MD5SUM="6c5ce0aa586019ec88ebfdae122157aa"
DOWNLOAD_x86_64=""
MD5SUM_x86_64=""
REQUIRES=""
MAINTAINER="William PC"
EMAIL="w_calandrini[at]hotmail[dot]com"