slackbuilds_ponce/academic/verilog
2010-05-19 02:30:53 -04:00
..
README academic/verilog: Added to 13.0 repository 2010-05-13 00:57:23 +02:00
slack-desc academic/verilog: Added to 13.0 repository 2010-05-13 00:57:23 +02:00
verilog.info academic/verilog: Added to 13.0 repository 2010-05-13 00:57:23 +02:00
verilog.SlackBuild academic/verilog: Fixed for bash4. 2010-05-19 02:30:53 -04:00

Icarus Verilog is a Verilog simulation and synthesis tool.  It operates as
a compiler, compiling source code written in Verilog (IEEE-1364) into some 
target format.  For batch simulation, the compiler can generate an intermediate
form called vvp assembly.  This intermediate form is executed by the 'vvp' 
command.  For synthesis, the compiler generates netlists in the desired format.