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19 lines
1 KiB
Text
19 lines
1 KiB
Text
# HOW TO EDIT THIS FILE:
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# The "handy ruler" below makes it easier to edit a package description.
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# Line up the first '|' above the ':' following the base package name, and
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# the '|' on the right side marks the last column you can put a character in.
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# You must make exactly 11 lines for the formatting to be correct. It's also
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# customary to leave one space after the ':' except on otherwise blank lines.
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|-----handy-ruler------------------------------------------------------|
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verilator: verilator (the fastest free Verilog HDL simulator)
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verilator:
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verilator: Verilator is invoked with parameters similar to GCC or Synopsys's
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verilator: VCS. It "Verilates" the specified synthesizable Verilog or
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verilator: SystemVerilog code by reading it, performing lint checks, and
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verilator: optionally inserting assertion checks and coverage-analysis points.
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verilator: It outputs single- or verilator: multi-threaded .cpp and .h files,
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verilator: the "Verilated" code.
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verilator:
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verilator: homepage: https://www.veripool.org/wiki/verilator
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verilator:
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