slackbuilds_ponce/academic/DRAMSim2

  DRAMSim2 is a cycle accurate model of a DRAM memory controller, the
DRAM modules which comprise system storage, and the bus by which they
communicate. All major components in a modern memory system are
modeled as their own respective objects within the source, including:
ranks, banks, command queue, the memory controller, etc.

For setting the DEBUG mode use the enviroment variable DEBUG=1