mirror of
https://github.com/Ponce/slackbuilds
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143991a46e
This field used to make sense in our pre-git days, but the Signed-Off-By: line serves the same purpose (and even more) now, so APPROVED has been rejected. ;-) Signed-off-by: Robby Workman <rworkman@slackbuilds.org> |
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| README | ||
| slack-desc | ||
| verilog.info | ||
| verilog.SlackBuild | ||
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the 'vvp' command. For synthesis, the compiler generates netlists in the desired format.