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7 lines
451 B
Text
7 lines
451 B
Text
DRAMsim3 models the timing paramaters and memory controller behavior
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for several DRAM protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5,
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GDDR6, HBM, HMC, STT-MRAM. It is implemented in C++ as an objected
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oriented model that includes a parameterized DRAM bank model, DRAM
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controllers, command queues and system-level interfaces to interact
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with a CPU simulator (GEM5, ZSim) or trace workloads. It is designed
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to be accurate, portable and parallel.
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