academic/verilator: Make slack-desc ASCII.

Signed-off-by: B. Watson <yalhcru@gmail.com>
This commit is contained in:
B. Watson 2022-03-15 11:27:07 -04:00
parent 44dcfc2a85
commit 2b96e2027e

View file

@ -8,7 +8,7 @@
|-----handy-ruler------------------------------------------------------|
verilator: verilator (the fastest free Verilog HDL simulator)
verilator:
verilator: Verilator is invoked with parameters similar to GCC or Synopsyss
verilator: Verilator is invoked with parameters similar to GCC or Synopsys's
verilator: VCS. It "Verilates" the specified synthesizable Verilog or
verilator: SystemVerilog code by reading it, performing lint checks, and
verilator: optionally inserting assertion checks and coverage-analysis points.